[ Cc added to authors of s3c2410_udc.c ]
Andy Green <[email protected]> writes:
> Somebody in the thread at some point said:
>
> | "USB device controller allows bulk transfer with DMA, interrupt and
> | control transfer."
> |
> | However, the document does not mention interrupt transfers anywhere
> | else and IN_CSR2_REG, bit ISO, makes me think that maybe only bulk
> | transfers are possible:
>
> The docs repeatedly say that interrupt transfer is supported... but I
> don't know enough about it to know how. I guess maybe you get further
> examining the udc driver looking for APIs around it?
I read through drivers/usb/gadget/s3c2410_udc.c but could not spot
anything obvious. arch/arm/plat-s3c24xx/include/plat/regs-udc.h
defines S3C2410_UDC_ICSR2_ISO but nothing seems to use it.
Just to have something to compare against I also read
drivers/usb/gadget/omap_udc.c which does talk about interrupt
transfers when it calls
#define OMAP_INT_EP(name,addr, maxp) \
buf = omap_ep_setup(name "-int", addr, \
USB_ENDPOINT_XFER_INT, buf, maxp, 0);
which just puts the endpoint type to bmAttributes but I can't see
where that would be sent to
hardware. http://www.ti.com/lit/gpn/omap5910 says "The exact endpoint
configuration is software-programmable." but does not elaborate
further what this means. Does the hardware read it from the
descriptor? Where is the descriptor sent to hardware?
best regards,
Timo Lindfors
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