Added commment on why I'm using BSP_fatal_exit instead of bsp_fatal and that it is required to flush the instruction cache also in single processor configuration.
Rewrote cache manager so that it announces the operation and then releases the lock to avoid deadlocks. Added test program that invokes the SMP cache management functions with ISR disabled and with the giant lock taken. _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
