On 8/11/2015 2:06 PM, Rohini Kulkarni wrote:
Hi, I would have to register the related mailbox interrupt and associate it with a handler that should be same as _SMP_Inter_processor_interrupt_handler(). Am I right?
That sounds correct.
From where can I get a reference of how to do this?
I would look at the Xilinx code that registers interrupts. The API should be the same. Also the clock driver, etc. The actual handler and IRQ number will vary.
On 11 Aug 2015 00:41, "Joel Sherrill" <joel.sherr...@oarcorp.com <mailto:joel.sherr...@oarcorp.com>> wrote: The source for the CPU supplement is in doc/cpu_supplement in the RTEMS tree. I do not know when the latest online was built so reading it there is probably safest. To build it, you will likely have to install some texinfo and texlive tools. cd $r/doc ../bootstrap cd ../.. mkdir b-doc cd b-doc $r/doc/configure --enable-maintainer-mode \ --prefix=DIRECTORY make make install That should be similar to how it is built. --joel On 8/10/2015 1:35 PM, Rohini Kulkarni wrote: The documentation that Sebastian was referring to. On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber <sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de> <mailto:sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de>>> wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, "IPI", RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. What is the CPU Architecture Supplement? You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. Thanks. On Wed, Jul 22, 2015 at 7:08 PM, Rohini Kulkarni <krohini1...@gmail.com <mailto:krohini1...@gmail.com> <mailto:krohini1...@gmail.com <mailto:krohini1...@gmail.com>> <mailto:krohini1...@gmail.com <mailto:krohini1...@gmail.com> <mailto:krohini1...@gmail.com <mailto:krohini1...@gmail.com>>>> wrote: Ok. Qemu suggestion seems helpful for the cache configuration issue though. I am trying with Pi 1. Thanks. On 22 Jul 2015 18:59, "Sebastian Huber" <sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de> <mailto:sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de>> <mailto:sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de> <mailto:sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de>>>> wrote: Sorry, I cannot help you here since I never worked with a Raspberry Pi. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de> <mailto:sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de>> <mailto:sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de> <mailto:sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de>>> PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Rohini Kulkarni -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de> <mailto:sebastian.hu...@embedded-brains.de <mailto:sebastian.hu...@embedded-brains.de>> PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Rohini Kulkarni -- Joel Sherrill, Ph.D. Director of Research & Development joel.sherr...@oarcorp.com On-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available (256) 722-9985
-- Joel Sherrill, Ph.D. Director of Research & Development joel.sherr...@oarcorp.com On-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available (256) 722-9985 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
