On Fri, Aug 28, 2015 at 2:31 PM, sudarshan.rajagopalan <sudarshan.rajagopa...@vecna.com> wrote: > On 2015-08-28 12:18, sudarshan.rajagopalan wrote: >> >> On 2015-08-28 11:30, Daniel Gutson wrote: >>> >>> On Fri, Aug 28, 2015 at 12:20 PM, Gedare Bloom <ged...@gwu.edu> wrote: >>>> >>>> Could you please open a ticket on our trac to describe the problem >>>> this fixes, and add "closes #xxxx." to your patch commit message? >> >> >> Hi Gedare, Sure will do! >> >>> >>> Additionally, please clarify which architecture this applies to. I >>> suspect this is for cortex-m4. >>> In any case, please clarify which architectures you tested on. We can >>> analyze and test cortex-m3 if you don't have one. >> >> >> Daniel, I've tested it on Cortex-M4 but this patch should also apply >> to Cortex-M3 or all ARMv7M based processor (including M7). But please >> feel free to test it on Cortex-M3 since I don't have it with me now. >> >> Am also attaching the links to ARM Cortex-M3, M4 and M7 Exception >> entry and return referenece documents for a quick reference, where the >> table gives all the possible exception error codes returned and which >> SP to pick depending on the error code. The only tricky part would be >> error code: 0xFFFFFFE1. But the asm "tst.w lr, #4" with lr=0xFFFFFFE1 >> will result into zero and will set the Zero flag, which will make the >> ITT EQ block execute, which will choose MSP, which it should for the >> return code 0xFFFFFFE1 (or even 0xFFFFFFF1) in all M3, M4 and M7. But >> please feel free to test it on real M3 an M7 processor. I have tested >> it by manually giving all the return error codes for M3 and M7 to LR >> and and it chooses the right SP value. >> >> ARM Reference Docs - Exception Entry and Return: >> C-3: >> >> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Babefdjc.html >> C-4: >> >> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/Babefdjc.html >> C-7: >> >> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0646a/Babefdjc.html >> >> Thanks and Regards, >> Sudarshan > > > > Ok, so we tested the fix on Cortex-M7 processor. The error codes for C-4 and > C-7 are all pretty much the same. This leaves with C-3, which I believe > should work too, becasue non-FPU error codes are same for C-3, C-4 and C-7.
Hi Sudarshan, ok thanks. We will comment on Monday since we have a release today. Good job. Daniel. > > Thanks, > > Sudarshan >> >> >>> >>>> >>>> Thanks, >>>> Gedare >>>> >>>> On Thu, Aug 27, 2015 at 4:33 PM, sudarshan.rajagopalan >>>> <sudarshan.rajagopa...@vecna.com> wrote: >>>>> >>>>> Patch attached here for ARMv7M Exception Handler. Looks like git >>>>> send-email >>>>> didn't deliver the mail. Something is not quite right with our mail >>>>> server >>>>> here. Avoid this email if patch delivered through git. >>>>> >>>>> Thanks and Regards, >>>>> >>>>> Sudarshan >>>>> >>>>> >>>>> >>>>> >>>>> _______________________________________________ >>>>> devel mailing list >>>>> devel@rtems.org >>>>> http://lists.rtems.org/mailman/listinfo/devel >>>> >>>> _______________________________________________ >>>> devel mailing list >>>> devel@rtems.org >>>> http://lists.rtems.org/mailman/listinfo/devel >> >> >> _______________________________________________ >> devel mailing list >> devel@rtems.org >> http://lists.rtems.org/mailman/listinfo/devel > > -- Daniel F. Gutson Chief Engineering Officer, SPD San Lorenzo 47, 3rd Floor, Office 5 Córdoba, Argentina Phone: +54 351 4217888 / +54 351 4218211 Skype: dgutson LinkedIn: http://ar.linkedin.com/in/danielgutson _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
