From: Pavel Pisa <[email protected]>
Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.
---
cpukit/score/cpu/arm/rtems/score/arm.h | 4 ++++
cpukit/score/cpu/arm/rtems/score/cpu.h | 7 +++++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h
b/cpukit/score/cpu/arm/rtems/score/arm.h
index 334e73a..9ae7830 100644
--- a/cpukit/score/cpu/arm/rtems/score/arm.h
+++ b/cpukit/score/cpu/arm/rtems/score/arm.h
@@ -54,6 +54,10 @@ extern "C" {
#define ARM_MULTILIB_HAS_THREAD_ID_REGISTER
#endif
+#if defined(__ARM_ARCH_7A__)
+ #define ARM_MULTILIB_CACHE_LINE_MAX_64B
+#endif
+
#if !defined(__SOFTFP__)
#if defined(__ARM_NEON__)
#define ARM_MULTILIB_VFP_D32
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h
b/cpukit/score/cpu/arm/rtems/score/cpu.h
index 91e4ec6..68ea178 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -145,8 +145,11 @@
#define CPU_STACK_GROWS_UP FALSE
-/* FIXME: Is this the right value? */
-#define CPU_CACHE_LINE_BYTES 32
+#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64B)
+ #define CPU_CACHE_LINE_BYTES 32
+#else
+ #define CPU_CACHE_LINE_BYTES 64
+#endif
#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
--
1.9.1
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