Hi Denis, Yes, I'm willing to fix these, just need time. Shouldn't be that difficult.
You can get more details on RISC-V assembly reading RISC-V specs (especially user-level spec) [1]. For example/references, you may have a look at the riscv-linux and/or seL4 ports [2, 3] (though, you've to be aware of 64-bit vs 32-bit differences). You shouldn't need to write lots of assembly code though. [1] https://riscv.org/specifications/ [2] https://github.com/riscv/riscv-linux/tree/priv-1.10/arch/riscv/kernel [3] https://github.com/heshamelmatary/seL4/tree/RISCVUnofficialRelease-03062017/src/arch/riscv On Mon, Jun 5, 2017 at 7:21 AM, Denis Obrezkov <denisobrez...@gmail.com> wrote: > 2017-06-05 0:14 GMT+03:00 Hesham Almatary <heshamelmat...@gmail.com>: >> >> Hi Denis, >> >> Yes, the Host-Target-Interface (HTIF) has been refactored/removed in >> RISC-V. Also, it was meant to work with riscv front-end server >> (riscv-fesvr) which is not the case for your HiFive BSP I guess. >> >> I believe now it's the good time for you to start creating your own >> HiFive BSP. You'll have to read/know how to output data over the >> HiFive serial port or so, and develop your own console driver for the >> board. You might find this link useful [1] when creating a new BSP, >> and also use other BSPs as a reference (e.g. riscv_generic). Main >> things to be aware of when creating a new BSP are: 1) startup code, 2) >> console driver, and 3) timer driver. To make things easier for you, >> and to give you credit for your contributions when merged upstream, >> you'd want to create a new branch for your HiFive BSP based on >> priv-1.10, and rebase against it when/if I make changes to it. >> >> Keep the good work up. >> >> [1] https://devel.rtems.org/wiki/TBR/UserManual/Submitting_a_BSP >> >> Best, >> Hesham >> >> On Mon, Jun 5, 2017 at 7:00 AM, Denis Obrezkov <denisobrez...@gmail.com> >> wrote: >> > 2017-06-04 16:17 GMT+03:00 Denis Obrezkov <denisobrez...@gmail.com>: >> >> >> >> Now I have a problem with console-io.c file. >> >> The problem is with csr macros - there is no more such a register >> >> "tohost". >> >> Here it is described a little: >> >> https://github.com/riscv/riscv-pk/issues/25 >> >> >> >> Could you explain what should be done here and what for was mtohost >> >> register? >> >> >> > >> > I have built riscv-generic bsp. Though there are a lot of warnings. >> > The current issue is that asm functions should be reimplemented (there >> > is no >> > more >> > such a register 'mtohost' in csr). >> > >> > -- >> > Regards, Denis Obrezkov >> >> >> >> -- >> Hesham > > > Thanks Hasham, > will you be able to fix these asm functions to make BSP work in SPIKE > simulator? > > Could you also point me to the good reference on risc-v assembler and about > assembler writing in general (for RISC) - I am not really good in it. > > -- > Regards, Denis Obrezkov -- Hesham _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel