Good job Sichen. Keep it up
On Sat, Jun 17, 2017 at 8:01 PM, Sichen Zhao <1473996...@qq.com> wrote:
> Enable/disable vector routines now check for a valid vector.
> Without these guards, the enable/disable vector routines
> will not work with the interrupt server.
> ---
> c/src/lib/libbsp/arm/beagle/irq.c | 22 ++++++++++++++--------
> 1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/c/src/lib/libbsp/arm/beagle/irq.c
> b/c/src/lib/libbsp/arm/beagle/irq.c
> index d080a5e..35750ba 100644
> --- a/c/src/lib/libbsp/arm/beagle/irq.c
> +++ b/c/src/lib/libbsp/arm/beagle/irq.c
> @@ -98,11 +98,14 @@ static uint32_t omap_get_mir_reg(rtems_vector_number
> vector, uint32_t *const mas
> rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
> {
> uint32_t mask, cur;
> - uint32_t mir_reg = omap_get_mir_reg(vector, &mask);
>
> - cur = mmio_read(omap_intr.base + mir_reg);
> - mmio_write(omap_intr.base + mir_reg, cur & ~mask);
> - flush_data_cache();
> + if (bsp_interrupt_is_valid_vector(vector)) {
> + uint32_t mir_reg = omap_get_mir_reg(vector, &mask);
> +
> + cur = mmio_read(omap_intr.base + mir_reg);
> + mmio_write(omap_intr.base + mir_reg, cur & ~mask);
> + flush_data_cache();
> + }
>
> return RTEMS_SUCCESSFUL;
> }
> @@ -110,11 +113,14 @@ rtems_status_code
> bsp_interrupt_vector_enable(rtems_vector_number vector)
> rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
> {
> uint32_t mask, cur;
> - uint32_t mir_reg = omap_get_mir_reg(vector, &mask);
>
> - cur = mmio_read(omap_intr.base + mir_reg);
> - mmio_write(omap_intr.base + mir_reg, cur | mask);
> - flush_data_cache();
> + if (bsp_interrupt_is_valid_vector(vector)) {
> + uint32_t mir_reg = omap_get_mir_reg(vector, &mask);
> +
> + cur = mmio_read(omap_intr.base + mir_reg);
> + mmio_write(omap_intr.base + mir_reg, cur | mask);
> + flush_data_cache();
> + }
>
> return RTEMS_SUCCESSFUL;
> }
> --
> 2.7.4
>
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