On 22/05/2019 22:34, Jiri Gaisler wrote:
Adding a pseudo-random delay of 0 - 15 clocks to each trap/interrupt causes the test to pass on all cpu configurations with the default time slice (50)..! I am not sure what this means - it could be a hidden race condition, the algorithm might need some jitter to work or it could still be a simulator issue.
Adding a pseudo-random delay to interrupts is probably not enough. Sometimes the atomic instructions are carried out with interrupts disabled. Would it be possible to add a pseudo-random delay to each of the instruction cycles per core?
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