Hi all, Hope you all are well. I guess this patch was missed for review. Requesting you to please provide more feedback as I continue to work to close #3905. I built the doc locally and it was working fine.
Thanks Mritunjay On Tue, Apr 14, 2020 at 12:39 AM Mritunjay <mritunjaysharma...@gmail.com> wrote: > Tried to fix the patch as per suggestions. Please review. > --- > user/bsps/bsps-m68k.rst | 1048 ++++++++++++++++++++++++++++++++++----- > 1 file changed, 924 insertions(+), 124 deletions(-) > > diff --git a/user/bsps/bsps-m68k.rst b/user/bsps/bsps-m68k.rst > index bdb516b..5ca9079 100644 > --- a/user/bsps/bsps-m68k.rst > +++ b/user/bsps/bsps-m68k.rst > @@ -8,7 +8,22 @@ m68k (Motorola 68000 / ColdFire) > av5282 > ====== > > -TODO. > +Overview > +-------- > + > +The Freescale ColdFire Evaluation Board provides a reference platform for > +engineers to develop a variety of embedded processing applications > requiring > +networking connectivity. The board hosts all the necessary hardware and > firmware > +needed to implement a networked interface using the Freescale MCF5282 > processor. > +By including all the necessary physical layer (PHY) devices, memory and > external > +expansion capability the designer can implement any bridging application > that > +requires 10/100 Ethernet, UARTs, CAN interface, QSPI, analog inputs and/or > +memory-mapped peripherals. The AvBus expansion connector allows for user > defined > +add-on hardware, or can be utilized with over 20 compatible evaluation and > +development boards from Avnet Electronics Marketing. These boards can be > mixed > +and matched to provide a variety of additional hardware and firmware > capability > +from PCI and PCI-X connectivity, RapidIO, memory and communications and > +video/audio functions. > > csb360 > ====== > @@ -18,27 +33,365 @@ TODO. > gen68340 > ======== > > -TODO. > +Overview > +-------- > + > +The MC68340 is a high-performance 32-bit integrated processor with direct > memory > +access (DMA), combining an enhanced M68000-compatible processor, 32-bit > DMA, and > +other peripheral subsystems on a single integrated circuit. The MC68340 > CPU32 > +delivers 32-bit CISC processor performance from a lower cost 16-bit memory > +system. The combination of peripherals offered in the MC68340 can be > found in a > +diverse range of microprocessor-based systems.Systems requiring very > high-speed > +block transfers of data can benefit from the MC68340. > + > +Organization > +------------ > + > +The M68300 family of integrated processors and controllers is built on an > M68000 > +core processor, an on-chip bus, and a selection of intelligent peripherals > +appropriate for a set of applications. The CPU32 is a powerful central > +processor with nearly the performance of the MC68020. A system integration > +module incorporates the external bus interface and many of the smaller > circuits > +that typically surround a microprocessor for address decoding, wait-state > +insertion, interrupt prioritization, clock generation, arbitration, > watchdog > +timing, and power-on reset timing. Each member of the M68300 family is > +distinguished by its selection of peripherals. Peripherals are chosen to > address > +specific applications but are often useful in a wide variety of > applications. > +The peripherals may be highly sophisticated timing or protocol engines > that have > +their own processors, or they may be more traditional peripheral > functions, such > +as UARTs and timers. Since each major function is designed in a standalone > +module, each module might be found in many different M68300 family parts. > + > +Architecture > +------------ > + > +The CPU32 is upward source- and object-code compatible with the MC68000 > and > +MC68010. It is downward source- and object-code compatible with the > MC68020. > +Within the M68000 family, architectural differences are limited to the > +supervisory operating state. User state programs can be executed > unchanged on > +upward-compatible devices. The major CPU32 features are as follows: > + > +* 32-Bit Internal Data Path and Arithmetic Hardware > +* 32-Bit Address Bus Supported by 32-Bit Calculations > +* Rich Instruction Set > +* Eight 32-Bit General-Purpose Data Registers > +* Seven 32-Bit General-Purpose Address Registers > +* Separate User and Supervisor Stack Pointers > +* Separate User and Supervisor State Address Spaces > +* Separate Program and Data Address Spaces > +* Many Data Types > +* Flexible Addressing Modes > +* Full Interrupt Processing > +* Expansion Capability > + > +The CPU32 is an M68000 family processor specially designed for use as a > 32-bit > +core processor and for operation over the intermodule bus (IMB). > Designers used > +the MC68020 as a model and included advances of the later M68000 family > +processors, resulting in an instruction execution performance of 4 MIPS > +(VAX-equivalent) at 25.16 MHz. The powerful and flexible M68000 > architecture is > +the basis of the CPU32. MC68000 (including the MC68HC000 and the > MC68EC000) and > +MC68010 user programs will run unmodified on the CPU32. The programmer > can use > +any of the eight 32-bit data registers for fast manipulation of data and > any of > +the eight 32-bit address registers for indexing data in memory. The CPU32 > can > +operate on data types of single bits, binary-coded decimal (BCD)digits, > and 8, > +16, and 32 bits. Peripherals and data in memory can reside anywhere in the > +4-Gbyte linear address space. A supervisor operating mode protects > system-level > +resources from the more restricted user mode, allowing a true virtual > +environment to be developed. > + > +Physical > +-------- > + > +The MC68340 is available as 0–16.78 MHz and 0–25.16 MHz, 0°C to +70°C and > +-40°C to +85°C, and 5.0 V ±5% and 3.3 V ±0.3 supply voltages (reduced > +frequencies at 3.3 V). Thirty-two power and ground leads minimize ground > bounce > +and ensure proper isolation of different sections of the chip, including > the > +clock oscillator. A 144 pins are used for signals and power. The MC68340 > is > +available in a gull-wing ceramic quad flat pack (CQFP) with 25.6-mil > (0.001-in) > +lead spacing or a 15 ´ 15 plastic pin grid array (PPGA) with 0.1-in pin > spacing. > + > +System Integration Module > +------------------------- > + > +The MC68340 SIM40 provides the external bus interface for both the CPU32 > and the > +DMA. It also eliminates much of the glue logic that typically supports the > +microprocessor and its interface with the peripheral and memory system. > The > +SIM40 provides programmable circuits to perform address decoding and chip > +selects, wait-state insertion, interrupt handling, clock generation, bus > +arbitration, watchdog timing, discrete I/O, and power-on reset timing. A > +boundary scan test capability is also provided. > + > +External Bus Interface > +---------------------- > + > +The external bus interface (EBI) handles thetransfer of information > between the > +internal CPU32 or DMA controller and memory, peripherals, or other > processing > +elements in the external address space. Based on the MC68030 bus, the > external > +bus provides up to 32 address lines and 16 data lines. Address extensions > +identify each bus cycle as CPU32 or DMA initiated, supervisor or user > privilege > +level, and instruction or data access. The data bus allows dynamic sizing > for > +8- or 16-bit bus accesses (plus 32 bits for DMA). Synchronous transfers > from the > +CPU32 or the DMA can be made in as little as two clock cycles. > + > +Clock Synthesizer > +----------------- > + > +The clock synthesizer generates the clock signals used by all internal > +operations as well as a clock output used by external devices. The clock > +synthesizer can operate with an inexpensive 32768-Hz watch crystal or an > +external oscillator for reference, using an internal phase-locked loop and > +voltage-controlled oscillator. At any time, software can select > +clock frequencies from 131 kHz to 16.78 MHz or 25.16 MHz, favoring either > low > +power consumption or high performance. Alternately, an external clock can > drive > +the clock signal directly at the operating frequency. With its fully > static > +HCMOS design, it is possible to completely stop the system clock without > losing > +the contents of the internal registers. > > gen68360 > ======== > > -TODO. > +Overview > +-------- > + > +The MC68360 Quad Integrated Communication Controller (QUICC) is a > versatile > +one-chip integrated microprocessor and peripheral combination family that > can be > +used in a variety of controller applications. > + > +The MC68360 particularly excels in communications activities. The QUICC > can be > +described as a next-generation MC68302, with higher performance in all > areas of > +device operation, increased flexibility, and higher integration. The term > "quad" > +comes from the fact that there are four serial communications controllers > +(SCCs) on the device. However, there are actually seven serial channels > which > +include four SCCs, two serial management controllers (SMCs), and one > serial > +peripheral interface (SPI). > + > +Features > +-------- > +CPU + Processor (8.3 MIPS at 33MHz) > + > +* 32-bit version of the CPU32 core (fully compatible with CPU32) > +* Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-Bits) + 32 > Address > + Lines > +* Complete static design (0-33 MHz Operation) > +* Slave mode to disable CPU32+ (allows use with external processors) > + * Multiple QUICCs can share one system bus (one master) > + * MC68040 companion mode allows QUICC to be an MC68040 companion > chip and > + intelligent peripheral (29 MIPS at 33 MHz) > + * All QUICC features available in slave mode > +* Memory controller (eight banks) > + * Contains complete Dynamic Random-Access Memory (DRAM) controller > + * Glueless interface to DRAM Single In-Line Memory Modules > (SIMMs), Static > + Random-Access Memory (SRAM) > + * Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, > etc. > + * Boot chip select available at Reset (options for 8-, 16-, or > 32-bit > + memory) > + * Special features for MC68040 including Burst Mode > +* Four general-purpose timers > + * Four 16-bit timers or two 32-bit timers > +* Two Independent DMAs (IDMAs) > +* System Integration Module (SIM60) > + * Bus monitor > + * Breakpoint logic provides on-chip H/W breakpoints > + * Spurious interrupt monitor > + * External masters may use on-chip features such as chip selects > +* Periodic interrupt timer > +* On-chip bus arbitration with no overhead for internal masters > +* Low power stop mode > +* IEEE 1149.1 Test Access Port > +* RISC Communications Processor Module (CPM) > +* Many new commands (e.g., Graceful Stop Transmit, Close RxBD) > +* Supports continuos mode transmission and reception on all serial > channels > +* 2.5 kbytes of dual-port RAM > +* 14 Serial DMA (SDMA) channels > +* Three parallel I/O registers with open-drain capability > +* Each serial channel can have its own Pins (NMSI mode) > +* Four baud rate generators > +* Four SCCs > +* Ethernet/IEEE 802.3 optional on SCCs 1-2@25 MHz, SCCs 1-3@33 MHz > +* HDLC Bus > +* Universal Asynchronous Receiver Transmitter (UART) > +* Synchronous UART > +* Asynchronous HDLC (RAM microcode option) to support PPP (Point to Point > + Protocol) > +* Two SMCs > +* UART > +* Transparent > +* General Circuit Interface (GCI) controller > +* One SPI > +* Time-Slot assignor > +* Supports two TDM channels > +* Parallel Interface Port (supports fast connection between QUICCs) > + > +Host controlled Board Setup > +--------------------------- > + > +Required equipment: > + > +* +5 V 5 A power supply > +* +12 V 1 A power supply (optional) > +* Host Computer, one of the following: > +* Sun - 4 (SBus interface) > +* IBM-PC/XT/AT > +* ADI board - compatible with the host computer > +* 37 line flat cable with female 37 pin D-type connectors on each end > + > +Stand alone Board Setup > +----------------------- > + > +Required equipment: > + > +* +5 V 5 A power supply > +* +12 V 1 A power supply (optional) > +* VT100 compatible terminal > +* RS-232 cable with male 9 pin D-type connector on the QUADS side. > + > +Debugging BDM controller > +------------------------ > + > +The slave QUICC enables the M68360QUADS to become BDM controller to > control > +other QUICC devices on the user application. The BDM feature enables the > user to > +download code and provides hardware and software debugging capability of > the > +user application. The 8 pin BDM connector P9 utilizes five pins of the > slave > +QUICC port B. These pins are configured as general purpose I/O pins. > + > +Debugging Ethernet controller > +----------------------------- > + > +The slave QUICC provides Ethernet port for the M68360QUADS by connecting > SCC1 to > +Motorola MC68160 EEST device (U35 in sheet 10). The MC68160 provides two > +Ethernet interfaces, twisted-pair on P8 and AUI on P7. The LEDs LD3-LD8 > are > +controlled by the EEST, and they provide indications about the status of > the > +Ethernet ports activity. The signals between the slave QUICC and the > MC68160 > +appear on connector P10 for debugging purposes. P10 is a set of wire > holes. > +The socket U24 is installed for internal factory testing only. For proper > +operation of the EEST, this socket must be empty. > + > +References > +---------- > + > +* `User Manual < > https://www.nxp.com/docs/en/reference-manual/MC68360UM.pdf>`_ > > genmcf548x > ========== > > -TODO. > +Overview > +-------- > + > +The MCF548x family is based on the ColdFire V4e core, a complex which > comprises > +the ColdFire V4 central processor unit (CPU), an enhanced > multiply-accumulate > +unit (EMAC), a memory management unit (MMU), a double-precision floating > point > +unit (FPU) conforming to standard IEEE-754, and controllers for caches > and local > +data memories. The MCF548x family is capable of performing at an operating > +frequency of up to 200 MHz or 308 MIPS. > + > +To maximize throughput, the MCF548x family incorporates three independent > +external bus interfaces: > + > +* The general-purpose local bus (FlexBus) is used for system boot > memories and > + simple peripherals and has up to six chip selects. > +* Program code and data can be stored in SDRAM connected to a dedicated > 32-bit > + double data rate (DDR) bus that can run at up to one-half of the CPU > core > + frequency. The glueless DDR SDRAM controller handles all address > multiplexing, > + input and output strobe timing, and memory bus clock generation. > +* A 32-bit PCI bus compliant with the version 2.2 specification and > running at > + a typical frequency of 25 MHz or 50 MHz supports peripherals that > require high > + bandwidth, the ability to arbitrate for bus mastership, and access to > internal > + MCF548x memory resources. > + > +References > +---------- > + > +* `User Manual < > https://www.nxp.com/docs/en/reference-manual/MCF5485RM.pdf>`_ > > mcf5206elite > ============ > > -TODO. > +Overview > +-------- > + > +The MCF5206e integrated microprocessor combines a Version 2 (V2) ColdFire > +processor core with several peripheral functions such as a DRAM > controller, > +timers, general-purpose I/O and serial interfaces, debug module, and > system > +integration. Designed for embedded control applications, the V2 ColdFire > core > +delivers enhanced performance while maintaining > +low system costs. To speed program execution, the largeon-chip > instruction cache > +and SRAM provide one-cycle access to critical code and data. The MCF5206e > +greatly reduces the time required for system design and implementation by > +packaging common system functions on chip and providing glueless > interfaces to 8 > +bit, 16 bit, and 32 bit DRAM, SRAM, ROM, and I/O devices. > + > +The MCF5206e is an enhanced version of the MCF5206 processor, with the > same > +peripheral set, DMA, MAC, Hardware Divide, larger cache, and larger SRAM. > It is > +pin compatible with the MCF5206, with the DMA pins muxed with Timer 0 > pins. > + > +References > +---------- > + > +* `User Manual < > https://www.nxp.com/docs/en/reference-manual/MCF5485RM.pdf>`_ > + > > mcf52235 > ======== > > -TODO. > +Overview > +-------- > + > +The MCF52235 represents a family of highly-integrated 32-bit > microcontrollers > +based on the V2 ColdFire microarchitecture. Featuring up to 32 Kbytes of > +internal SRAM and 256 Kbytes of flash memory, four 32-bit timers with DMA > +request capability, a 4-channel DMA controller, fast Ethernet controller, > +a CAN module, an I2C module, 3 UARTs and a queued SPI, the MC52235 family > has > +been designed for general-purpose industrial control applications. > + > +This 32-bit device is based on the Version 2 ColdFire core operating at a > +frequency up to 60 MHz, offering high performance and low power > consumption. > +On-chip memories connected tightly to the processor core include up to 256 > +Kbytes of Flash and 32 Kbytes of static random access memory (SRAM). > + > +This BSP was heavily based on the MCF5235 BSP. > + > +Key features > +------------ > + > +* Version 2 ColdFire variable-length RISC processor core > +* System debug support > +* On-chip memories > +* Power management > +* Fast Ethernet Controller (FEC) > +* On-chip Ethernet Transceiver (EPHY) > +* FlexCAN 2.0B module > +* Three universal asynchronous/synchronous receiver transmitters (UARTs) > +* I2C module > +* Queued serial peripheral interface (QSPI) > +* Fast analog-to-digital converter (ADC) > +* Four 32-bit DMA timers > +* Four-channel general purpose timers > +* Pulse-width modulation timer > +* Real-Time Clock (RTC) > +* Two periodic interrupt timers (PITs) > +* Software watchdog timer > +* Clock Generation Features > +* Dual Interrupt Controllers (INTC0/INTC1) > +* DMA controller > +* Reset > +* Chip integration module (CIM) > +* General purpose I/O interface > +* JTAG support for system level board testing > + > +Board Setup > +----------- > + > +To setup, we will display the firmware settings using the boot monitor's > "state" > +command: > + > +.. code-block:: none > + > + INET> state > + iface 0- IP addr:192.168.1.99 subnet:255.255.255.0 > gateway:192.168.1.1 > + current tick count 4204 > + Task wakeups:netmain: 27 > + nettick: 2102 > + keyboard: 2099 > > mcf5225x > ======== > @@ -48,7 +401,36 @@ TODO. > mcf5235 > ======= > > -TODO. > +Overview > +-------- > + > +The MCF5235EVB is a Motorola evaluation board that is based on the > Coldfire > +MCF5235 32-bit processor. The board includes 32 Mbytes of SDRAM, 2Mbytes > of > +flash, the MCF5235 processor with a max core frequency of 150MHz, Ethernet > +support, and CAN bus support. This BSP has also been tested to work with > the > +Coldfire MCF5270 processor with a max core frequency of 100MHz. > +This BSP has also been tested to work with the newer Freescale M5235BCC > +evaluation board and with the Axiom Manufacturing CMM-5235 Board. > +The BSP provides support to run applications from both RAM when debugging > and > +from Flash when the application is complete. > + > +Board Setup > +----------- > + > +Here is the setup for the Axiom M5235BCC in the RTEMS Lab: > + > +.. code-block:: none > + > + dBUG> show > + base: 16 baud: 19200 > + server: 192.168.1.92 client: 192.168.1.241 > + gateway: 192.168.1.14 netmask: 255.255.255.0 > + filename: /mcf5235.exe filetype: ELF > + ethaddr: 00:20:DD:00:00:11 > + > +Downloading and Executing > +------------------------- > + > > mcf5329 > ======= > @@ -75,12 +457,132 @@ TODO. > mvme147 > ======= > > -TODO. > +Overview > +-------- > + > +The MVME147 is a double-high VMEmodule based on the MC68030 > microprocessor. It > +is best utilized in a 32-bit VMEbus system with both P1 and P2 > backplanes. The > +module has high functionality with large onboard shared RAM, serial > ports, and > +Centronics printer port. The module provides a SCSI bus controller with > DMA, > +floating-point coprocessor, tick timer, watchdog timer, and time-of-day > +clock/calendar with battery backup, 4KB of static RAM with battery > backup, four > +ROM sockets, and A32/D32 VMEbus interface with system controller > functions. > + > +Key Features > +------------ > + > +* 16, 25, or 33.33 MHz MC68030 enhanced 32-bit microprocessor > +* 16, 25, or 33.33 MHz MC68882 floating-point coprocessor > +* 4, 8, 16, or 32MB of shared DRAM, with programmable parity > +* 4K x 8 SRAM and time-of-day clock with battery backup > +* Four 28/32-pin ROM/PROM/EPROM/EEPROM sockets, 16 bits wide > +* A32/D32 VMEbus master/slave interface with system controller function > +* Four EIA-232-D serial communications ports > +* Centronics compatible printer port > +* Two 16-bit timers and watchdog timer > +* SCSI bus interface with DMA > +* Ethernet transceiver interface > +* 4-level requester, 7-level interrupter, and 7-level interrupt handler > for > + VMEbus > +* On-board debugger and diagnostic firmware > + > +Board Setup > +----------- > + > +Set jumpers on your MVME147 module. Ensure that ROM devices are properly > +installed in the sockets. Install your MVME147 module in the chassis. Set > +jumpers on the transition board; connect and install the transition > board, P2 > +adapter module, and optional SCSI device cables. Connect a console > terminal to > +the MVME712. Connect any other optional devices or equipment you will be > using. > +Power up the system. Note that the debugger prompt appears. Initialize the > +clock. Examine and/or change environmental parameters. Program the > PCCchip and > +VMEchip. > + > +See `manual <ppd.fnal.gov/experiments/e907/TPC/DAQ/147aih.pdf>`_ for > further > +information. > + > +Downloading and Executing > +------------------------- > + > +There are various ways to enter a user program into system memory for > execution. > +One way is to create the program using the Memory Modify (MM) command > with the > +assembler/disassembler option. You enter the program one source line at a > time. > +After each source line is entered, it is assembled and the object code > loads > +into memory. Refer to the MVME147 BUG 147Bug Debugging Package User's > Manual for > +complete details of the 147Bug Assembler/Disassembler. Another way to > enter a > +program is to download an object file from a host system. The program > must be in > +S-record format (described in the MVME147BUG 147Bug Debugging Package > User's > +Manual) and may have been assembled or compiled on the host system. > Alternately, > +the program may have been previously created using the 147Bug MM command > as > +outlined above and stored to the host using the Dump (DU) command. A > +communication link must exist between the host system and the MVME147. > The file > +is downloaded from the host to MVME147 memory by the Load (LO) command. > + > +References > +---------- > + > +* `User Manual <ppd.fnal.gov/experiments/e907/TPC/DAQ/147aih.pdf>`_ > > mvme147s > ======== > > -TODO. > +Overview > +-------- > + > +The MVME 147s is extremely similar to the Mvme147. The main difference > between > +them is that the 147s also has only 2KB of static RAM while the 147 has > 4KB. > + > +Another small difference between them is the time-of-day clock. The > MVME147s has > +a Mostek MK48T02 while the MVME147 has an M48T18. > + > +The MVME147S is a double-high VMEmodule and is best utilized in a 32-bit > VMEbus > +system with both P1 and P2 backplanes. The module has high functionality > with > +large onboard shared RAM, serial ports, and Centronics printer port. The > module > +provides a SCSI bus controller with DMA, floating-point coprocessor, tick > timer, > +watchdog timer, and time-of-day clock/calendar with battery backup, 2KB of > +static RAM with battery backup, four ROM sockets, and A32/D32 VMEbus > interface > +with system controller functions are also provided. The MVME147S can be > operated > +as part of a VMEbus system with other VMEmodules such as RAM modules, CPU > +modules, graphics modules, and analog I/O modules. > + > +Board Setup > +----------- > + > +To select the desired configuration and ensure proper operation of the > MVME147S > +module, certain changes may be made before installation. These changes > are made > +through jumper arrangements on the headers. The module has been factory > tested > +and is shipped with factory-installed jumper configurations. The module is > +operational with the factory-installed jumpers. The module is configured > to > +provide the system functions required for a VMEbus system. It is > necessary to > +make changes in the jumper arrangements for the following conditions: > + > +System controller select (J3) Factory use only (J5, J6) ROM configuration > select > + (J1, J2) Serial port 4 clock configuration select (J8, J9) > + > +See `manual <www.ing.iac.es/~docs/external/vme/147s_d3.pdf>`_ for further > +information. > + > +Downloading and Executing > +------------------------- > + > +There are various ways to enter a user program into system memory for > execution. > +One way is to create the program using the Memory Modify (MM) command > with the > +assembler/disassembler option. You enter the program one source line at a > time. > +After each source line is entered, it is assembled and the object code > loads > +into memory. Refer to the MVME147 BUG 147Bug Debugging Package User's > Manual for > +complete details of the 147Bug Assembler/Disassembler. Another way to > enter a > +program is to download an object file from a host system. The program > must be in > +S-record format (described in the MVME147BUG 147Bug Debugging Package > User's > +Manual) and may have been assembled or compiled on the host system. > +Alternately, the program may have been previously created using the > 147Bug MM > +command as outlined above and stored to the host using the Dump (DU) > command. > +A communication link must exist between the host system and the MVME147. > The > +file is downloaded from the host to MVME147 memory by the Load (LO) > command. > + > +References > +---------- > + > +* `User Manual <www.ing.iac.es/~docs/external/vme/147s_d3.pdf>`_ > > mvme162 > ======= > @@ -112,99 +614,99 @@ The env settings are: > > MPU Clock Speed =25Mhz > 162-Bug>env > - Bug or System environment [B/S] = B? > - Field Service Menu Enable [Y/N] = N? > - Remote Start Method Switch [G/M/B/N] = B? > - Probe System for Supported I/O Controllers [Y/N] = Y? > - Negate VMEbus SYSFAIL* Always [Y/N] = N? > - Local SCSI Bus Reset on Debugger Startup [Y/N] = N? > - Local SCSI Bus Negotiations Type [A/S/N] = A? > - Industry Pack Reset on Debugger Startup [Y/N] = Y? > - Ignore CFGA Block on a Hard Disk Boot [Y/N] = Y? > - Auto Boot Enable [Y/N] = N? > - Auto Boot at power-up only [Y/N] = Y? > - Auto Boot Controller LUN = 00? > - Auto Boot Device LUN = 00? > - Auto Boot Abort Delay = 15? > - Auto Boot Default String [NULL for a empty string] = ? > - ROM Boot Enable [Y/N] = N? > - ROM Boot at power-up only [Y/N] = Y? > - ROM Boot Enable search of VMEbus [Y/N] = N? > - ROM Boot Abort Delay = 0? > - ROM Boot Direct Starting Address = FF800000? > - ROM Boot Direct Ending Address = FFDFFFFC? > - Network Auto Boot Enable [Y/N] = N? > - Network Auto Boot at power-up only [Y/N] = Y? > - Network Auto Boot Controller LUN = 00? > - Network Auto Boot Device LUN = 00? > - Network Auto Boot Abort Delay = 5? > - Network Auto Boot Configuration Parameters Pointer (NVRAM) = > FFE0FF00? > - Memory Search Starting Address = 00000000? > - Memory Search Ending Address = 01000000? > - Memory Search Increment Size = 00010000? > - Memory Search Delay Enable [Y/N] = N? > - Memory Search Delay Address = FFFFD20F? > - Memory Size Enable [Y/N] = Y? > - Memory Size Starting Address = 00000000? > - Memory Size Ending Address = 01000000? > - Base Address of Dynamic Memory = 00000000? > - Size of Parity Memory = 00000000? > - Size of ECC Memory Board #0 = 01000000? > - Size of ECC Memory Board #1 = 00000000? > - Base Address of Static Memory = FFE00000? > - Size of Static Memory = 00020000? > - Slave Enable #1 [Y/N] = Y? > - Slave Starting Address #1 = 00000000? > - Slave Ending Address #1 = 00FFFFFF? > - Slave Address Translation Address #1 = 00000000? > - Slave Address Translation Select #1 = 00000000? > - Slave Control #1 = 03FF? > - Slave Enable #2 [Y/N] = N? > - Slave Starting Address #2 = 00000000? > - Slave Ending Address #2 = 00000000? > - Slave Address Translation Address #2 = 00000000? > - Slave Address Translation Select #2 = 00000000? > - Slave Control #2 = 0000? > - Master Enable #1 [Y/N] = Y? > - Master Starting Address #1 = 01000000? > - Master Ending Address #1 = EFFFFFFF? > - Master Control #1 = 0D? > - Master Enable #2 [Y/N] = N? > - Master Starting Address #2 = 00000000? > - Master Ending Address #2 = 00000000? > - Master Control #2 = 00? > - Master Enable #3 [Y/N] = N? > - Master Starting Address #3 = 00000000? > - Master Ending Address #3 = 00000000? > - Master Control #3 = 00? > - Master Enable #4 [Y/N] = N? > - Master Starting Address #4 = 00000000? > - Master Ending Address #4 = 00000000? > - Master Address Translation Address #4 = 00000000? > - Master Address Translation Select #4 = 00000000? > - Master Control #4 = 00? > - Short I/O (VMEbus A16) Enable [Y/N] = Y? > - Short I/O (VMEbus A16) Control = 01? > - F-Page (VMEbus A24) Enable [Y/N] = Y? > - F-Page (VMEbus A24) Control = 02? > - ROM Access Time Code = 03? > - FLASH Access Time Code = 02? > - MCC Vector Base = 05? > - VMEC2 Vector Base #1 = 06? > - VMEC2 Vector Base #2 = 07? > - VMEC2 GCSR Group Base Address = D2? > - VMEC2 GCSR Board Base Address = 00? > - VMEbus Global Time Out Code = 01? > - Local Bus Time Out Code = 02? > - VMEbus Access Time Out Code = 02? > - IP A Base Address = 00000000? > - IP B Base Address = 00000000? > - IP C Base Address = 00000000? > - IP D Base Address = 00000000? > - IP D/C/B/A Memory Size = 00000000? > - IP D/C/B/A General Control = 00000000? > - IP D/C/B/A Interrupt 0 Control = 00000000? > - IP D/C/B/A Interrupt 1 Control = 00000000? > + Bug or System environment [B/S] = B > + Field Service Menu Enable [Y/N] = N > + Remote Start Method Switch [G/M/B/N] = B > + Probe System for Supported I/O Controllers [Y/N] = Y > + Negate VMEbus SYSFAIL* Always [Y/N] = N > + Local SCSI Bus Reset on Debugger Startup [Y/N] = N > + Local SCSI Bus Negotiations Type [A/S/N] = A > + Industry Pack Reset on Debugger Startup [Y/N] = Y > + Ignore CFGA Block on a Hard Disk Boot [Y/N] = Y > + Auto Boot Enable [Y/N] = N > + Auto Boot at power-up only [Y/N] = Y > + Auto Boot Controller LUN = 00 > + Auto Boot Device LUN = 00 > + Auto Boot Abort Delay = 15 > + Auto Boot Default String [NULL for a empty string] = > + ROM Boot Enable [Y/N] = N > + ROM Boot at power-up only [Y/N] = Y > + ROM Boot Enable search of VMEbus [Y/N] = N > + ROM Boot Abort Delay = 0 > + ROM Boot Direct Starting Address = FF800000 > + ROM Boot Direct Ending Address = FFDFFFFC > + Network Auto Boot Enable [Y/N] = N > + Network Auto Boot at power-up only [Y/N] = Y > + Network Auto Boot Controller LUN = 00 > + Network Auto Boot Device LUN = 00 > + Network Auto Boot Abort Delay = 5 > + Network Auto Boot Configuration Parameters Pointer (NVRAM) = > FFE0FF00 > + Memory Search Starting Address = 00000000 > + Memory Search Ending Address = 01000000 > + Memory Search Increment Size = 00010000 > + Memory Search Delay Enable [Y/N] = N > + Memory Search Delay Address = FFFFD20F > + Memory Size Enable [Y/N] = Y > + Memory Size Starting Address = 00000000 > + Memory Size Ending Address = 01000000 > + Base Address of Dynamic Memory = 00000000 > + Size of Parity Memory = 00000000 > + Size of ECC Memory Board #0 = 01000000 > + Size of ECC Memory Board #1 = 00000000 > + Base Address of Static Memory = FFE00000 > + Size of Static Memory = 00020000 > + Slave Enable #1 [Y/N] = Y > + Slave Starting Address #1 = 00000000 > + Slave Ending Address #1 = 00FFFFFF > + Slave Address Translation Address #1 = 00000000 > + Slave Address Translation Select #1 = 00000000 > + Slave Control #1 = 03FF > + Slave Enable #2 [Y/N] = N > + Slave Starting Address #2 = 00000000 > + Slave Ending Address #2 = 00000000 > + Slave Address Translation Address #2 = 00000000 > + Slave Address Translation Select #2 = 00000000 > + Slave Control #2 = 0000 > + Master Enable #1 [Y/N] = Y > + Master Starting Address #1 = 01000000 > + Master Ending Address #1 = EFFFFFFF > + Master Control #1 = 0D > + Master Enable #2 [Y/N] = N > + Master Starting Address #2 = 00000000 > + Master Ending Address #2 = 00000000 > + Master Control #2 = 00 > + Master Enable #3 [Y/N] = N > + Master Starting Address #3 = 00000000 > + Master Ending Address #3 = 00000000 > + Master Control #3 = 00 > + Master Enable #4 [Y/N] = N > + Master Starting Address #4 = 00000000 > + Master Ending Address #4 = 00000000 > + Master Address Translation Address #4 = 00000000 > + Master Address Translation Select #4 = 00000000 > + Master Control #4 = 00 > + Short I/O (VMEbus A16) Enable [Y/N] = Y > + Short I/O (VMEbus A16) Control = 01 > + F-Page (VMEbus A24) Enable [Y/N] = Y > + F-Page (VMEbus A24) Control = 02 > + ROM Access Time Code = 03 > + FLASH Access Time Code = 02 > + MCC Vector Base = 05 > + VMEC2 Vector Base #1 = 06 > + VMEC2 Vector Base #2 = 07 > + VMEC2 GCSR Group Base Address = D2 > + VMEC2 GCSR Board Base Address = 00 > + VMEbus Global Time Out Code = 01 > + Local Bus Time Out Code = 02 > + VMEbus Access Time Out Code = 02 > + IP A Base Address = 00000000 > + IP B Base Address = 00000000 > + IP C Base Address = 00000000 > + IP D Base Address = 00000000 > + IP D/C/B/A Memory Size = 00000000 > + IP D/C/B/A General Control = 00000000 > + IP D/C/B/A Interrupt 0 Control = 00000000 > + IP D/C/B/A Interrupt 1 Control = 00000000 > > To setup the Server/Client IP Addresses for the TFTP Transfer, we will > use the > NIOT command. NIOT (Network I/O Teach) is a 162-Bug's debugger command > commonly > @@ -215,26 +717,26 @@ The NIOT command goes something like this: > .. code-block:: none > > 162-Bug>niot > - Controller LUN =00? > - Device LUN =00? > - Node Control Memory Address =FFE10000? > - Client IP Address =192.168.1.245? > - Server IP Address =192.168.1.92? > - Subnet IP Address Mask =255.255.255.0? > - Broadcast IP Address =192.168.1.255? > - Gateway IP Address =0.0.0.0? > - Boot File Name ("NULL" for None) =/mvme162.img? > - Argument File Name ("NULL" for None) =? > - Boot File Load Address =00020000? > - Boot File Execution Address =00020000? > - Boot File Execution Delay =00000000? > - Boot File Length =00000000? > - Boot File Byte Offset =00000000? > - BOOTP/RARP Request Retry =00? > - TFTP/ARP Request Retry =00? > - Trace Character Buffer Address =00000000? > - BOOTP/RARP Request Control: Always/When-Needed (A/W)=A? > - BOOTP/RARP Reply Update Control: Yes/No (Y/N) =Y? > + Controller LUN =00 > + Device LUN =00 > + Node Control Memory Address =FFE10000 > + Client IP Address =192.168.1.245 > + Server IP Address =192.168.1.92 > + Subnet IP Address Mask =255.255.255.0 > + Broadcast IP Address =192.168.1.255 > + Gateway IP Address =0.0.0.0 > + Boot File Name ("NULL" for None) =/mvme162.img > + Argument File Name ("NULL" for None) = > + Boot File Load Address =00020000 > + Boot File Execution Address =00020000 > + Boot File Execution Delay =00000000 > + Boot File Length =00000000 > + Boot File Byte Offset =00000000 > + BOOTP/RARP Request Retry =00 > + TFTP/ARP Request Retry =00 > + Trace Character Buffer Address =00000000 > + BOOTP/RARP Request Control: Always/When-Needed (A/W)=A > + BOOTP/RARP Reply Update Control: Yes/No (Y/N) =Y > > Downloading and Executing > -------------------------- > @@ -264,9 +766,307 @@ The program will automatically run when download is > complete. > mvme167 > ======= > > -TODO. > +Overview > +-------- > + > +The MVME167 is a double-high VMEmodule based on the MC68040 > microprocessor.The > +MVME167 has 4/8/16/32/64 MB of parity-protected DRAM > or4/8/16/32/64/128/256 MB > +of ECC-protected DRAM, 8KB of static RAM and time of day clock (with > +battery backup), Ethernet transceiver interface, four serial ports with > +EIA-232-D interface, four tick timers, watchdog timer, four ROM sockets, > SCSI > +bus interface with DMA, Centronics printer port, > A16/A24/A32/D8/D16/D32/D64 > +VMEbus master/slave interface, 128KB of static RAM (with optional battery > +backup),and VMEbus system controller. > + > +Firmware Setup > +-------------- > + > +The mvme167 BSP by default (i.e., unless you tamper with the linkcmds) is > linked > +at 0x00800000 and the firmware has to be properly configured so that > loading and > +executing at that address is possible: # The board's RAM must be mapped > +starting at address 0x00800000 (and not zero as may seem more natural and > which > +IIRC is 167Bug's default). ## Use 167Bug's 'env' command to set the 'Base > +Address of Local Memory' to 00800000. ## Use 167Bug's 'niot' command to > set the > +download and execution address to 00800000. # By default, the 167Bug > firmware > +uses the lowest 64k block of RAM it finds for internal data and this > conflicts > +with RTEMS' needs. 167Bug won't allow you to download the RTEMS image to > +0x00800000 unless you instruct 167Bug to use another area (e.g., static > RAM) for > +it's internal data. ## Use 167Bug's 'env' command to set both, the 'Memory > +Search Starting Address' and 'Memory Search Ending Address' to zero. > +The 'search' area is the address-range that is scanned by 167Bug when it > tries > +to find an area for it's internal data. If it finds no RAM (since > start==end) > +then it uses static RAM and 00800000 and up can be used by RTEMS. > + > +These are the 'env' settings: > + > +.. code-block:: none > + > + MPU Clock Speed =25Mhz > + > + 167-Bug>env > + Bug or System environment [B/S] = B > + Field Service Menu Enable [Y/N] = N > + Remote Start Method Switch [G/M/B/N] = B > + Probe System for Supported I/O Controllers [Y/N] = Y > + Negate VMEbus SYSFAIL* Always [Y/N] = N > + Local SCSI Bus Reset on Debugger Startup [Y/N] = N > + Local SCSI Bus Negotiations Type [A/S/N] = A > + Ignore CFGA Block on a Hard Disk Boot [Y/N] = Y > + Auto Boot Enable [Y/N] = N > + Auto Boot at power-up only [Y/N] = Y > + Auto Boot Controller LUN = 00 > + Auto Boot Device LUN = 00 > + Auto Boot Abort Delay = 15 > + Auto Boot Default String [NULL for a empty string] = > + ROM Boot Enable [Y/N] = N > + ROM Boot at power-up only [Y/N] = Y > + ROM Boot Enable search of VMEbus [Y/N] = N > + ROM Boot Abort Delay = 0 > + ROM Boot Direct Starting Address = FF800000 > + ROM Boot Direct Ending Address = FFBFFFFC > + Network Auto Boot Enable [Y/N] = N > + Network Auto Boot at power-up only [Y/N] = Y > + Network Auto Boot Controller LUN = 00 > + Network Auto Boot Device LUN = 00 > + Network Auto Boot Abort Delay = 5 > + Network Auto Boot Configuration Parameters Pointer (NVRAM) = > FFFC0000 > + Memory Search Starting Address = 00000000 > + Memory Search Ending Address = 00000000 > + Memory Search Increment Size = 00010000 > + Memory Search Delay Enable [Y/N] = N > + Memory Search Delay Address = FFFFCE0F > + Memory Size Enable [Y/N] = Y > + Memory Size Starting Address = 00000000 > + Memory Size Ending Address = 01000000 > + Base Address of Local Memory = 00800000 > + Size of Local Memory Board #0 = 00800000 > + Size of Local Memory Board #1 = 00000000 > + Slave Enable #1 [Y/N] = Y > + Slave Starting Address #1 = 00000000 > + Slave Ending Address #1 = 007FFFFF > + Slave Address Translation Address #1 = 00000000 > + Slave Address Translation Select #1 = FF800000 > + Slave Control #1 = 00FF > + Slave Enable #2 [Y/N] = N > + Slave Starting Address #2 = FFE00000 > + Slave Ending Address #2 = FFE1FFFF > + Slave Address Translation Address #2 = 00000000 > + Slave Address Translation Select #2 = 00000000 > + Slave Control #2 = 01EF > + Master Enable #1 [Y/N] = Y > + Master Starting Address #1 = 01000000 > + Master Ending Address #1 = EFFFFFFF > + Master Control #1 = 0D > + Master Enable #2 [Y/N] = N > + Master Starting Address #2 = 00000000 > + Master Ending Address #2 = 00000000 > + Master Control #2 = 00 > + Master Enable #3 [Y/N] = N > + Master Starting Address #3 = 00800000 > + Master Ending Address #3 = 00FFFFFF > + Master Control #3 = 3D > + Master Enable #4 [Y/N] = N > + Master Starting Address #4 = 00000000 > + Master Ending Address #4 = 00000000 > + Master Address Translation Address #4 = 00000000 > + Master Address Translation Select #4 = 00000000 > + Master Control #4 = 00 > + Short I/O (VMEbus A16) Enable [Y/N] = Y > + Short I/O (VMEbus A16) Control = 01 > + F-Page (VMEbus A24) Enable [Y/N] = Y > + F-Page (VMEbus A24) Control = 02 > + ROM Speed Bank A Code = 05 > + ROM Speed Bank B Code = 05 > + Static RAM Speed Code = 01 > + PCC2 Vector Base = 05 > + VMEC2 Vector Base #1 = 06 > + VMEC2 Vector Base #2 = 07 > + VMEC2 GCSR Group Base Address = CC > + VMEC2 GCSR Board Base Address = 00 > + VMEbus Global Time Out Code = 01 > + Local Bus Time Out Code = 00 > + VMEbus Access Time Out Code = 02 > + 167-Bug> > + > +NIOT (Network I/O Teach) is a 167-Bug's debugger command commonly > +used to setup the Server/Client IP Addresses for the TFTP Transfer. > + > +The NIOT command goes something like this: > + > + > +.. code-block:: none > + > + 167-Bug>niot > + Controller LUN =00 > + Device LUN =00 > + Node Control Memory Address =FFE10000 > + Client IP Address =0.0.0.0 > + Server IP Address =0.0.0.0 > + Subnet IP Address Mask =0.0.0.0 > + Broadcast IP Address =0.0.0.0 > + Gateway IP Address =0.0.0.0 > + Boot File Name ("NULL" for None) = > + Argument File Name ("NULL" for None) = > + Boot File Load Address =00800000 > + Boot File Execution Address =00800000 > + Boot File Execution Delay =00000000 > + Boot File Length =00000000 > + Boot File Byte Offset =00000000 > + BOOTP/RARP Request Retry =00 > + TFTP/ARP Request Retry =00 > + Trace Character Buffer Address =00000000 > + BOOTP/RARP Request Control: Always/When-Needed (A/W)=A > + BOOTP/RARP Reply Update Control: Yes/No (Y/N) =Y > + 167-Bug> > + > +RTEMS Lab Board Setup > +--------------------- > + > +The firmware setup instructions above are true for the RTEMS Lab board > except > +for the memory search addresses. Set these as follows: > + > +.. code-block:: none > + > + Memory Search Starting Address = FFE00000 > + Memory Search Ending Address = FFE10000 > + > +These are the RTEMS Lab board settings: > + > +.. code-block:: none > + > + MPU Clock Speed =25Mhz > + > + 167-Bug>env > + Bug or System environment [B/S] = B > + Field Service Menu Enable [Y/N] = N > + Remote Start Method Switch [G/M/B/N] = B > + Probe System for Supported I/O Controllers [Y/N] = Y > + Negate VMEbus SYSFAIL* Always [Y/N] = N > + Local SCSI Bus Reset on Debugger Startup [Y/N] = N > + Ignore CFGA Block on a Hard Disk Boot [Y/N] = Y > + Auto Boot Enable [Y/N] = N > + Auto Boot at power-up only [Y/N] = Y > + Auto Boot Controller LUN = 00 > + Auto Boot Device LUN = 00 > + Auto Boot Abort Delay = 15 > + Auto Boot Default String [Y(NULL String)/(String)] = > + ROM Boot Enable [Y/N] = N > + ROM Boot at power-up only [Y/N] = Y > + ROM Boot Enable search of VMEbus [Y/N] = N > + ROM Boot Abort Delay = 0 > + ROM Boot Direct Starting Address = FF800000 > + ROM Boot Direct Ending Address = FFBFFFFC > + Network Auto Boot Enable [Y/N] = N > + Network Auto Boot at power-up only [Y/N] = N > + Network Auto Boot Controller LUN = 00 > + Network Auto Boot Device LUN = 00 > + Network Auto Boot Abort Delay = 5 > + Network Auto Boot Configuration Parameters Pointer (NVRAM) = > FFFC0000 > + Memory Search Starting Address = FFE00000 > + Memory Search Ending Address = FFE10000 > + Memory Search Increment Size = 00010000 > + Memory Search Delay Enable [Y/N] = N > + Memory Search Delay Address = FFFFCE0F > + Memory Size Enable [Y/N] = Y > + Memory Size Starting Address = 00000000 > + Memory Size Ending Address = 01000000 > + Base Address of Local Memory = 00800000 > + Size of Local Memory Board #0 = 01000000 > + Size of Local Memory Board #1 = 00000000 > + Slave Enable #1 [Y/N] = Y > + Slave Starting Address #1 = 00000000 > + Slave Ending Address #1 = 007FFFFF > + Slave Address Translation Address #1 = 00000000 > + Slave Address Translation Select #1 = FF800000 > + Slave Control #1 = 00FF > + Slave Enable #2 [Y/N] = N > + Slave Starting Address #2 = FFE00000 > + Slave Ending Address #2 = FFE10000 > + Slave Address Translation Address #2 = 00000000 > + Slave Address Translation Select #2 = 00000000 > + Slave Control #2 = 01EF > + Master Enable #1 [Y/N] = Y > + Master Starting Address #1 = 01000000 > + Master Ending Address #1 = EFFFFFFF > + Master Control #1 = 0D > + Master Enable #2 [Y/N] = N > + Master Starting Address #2 = 00000000 > + Master Ending Address #2 = 00000000 > + Master Control #2 = 00 > + Master Enable #3 [Y/N] = N > + Master Starting Address #3 = 00800000 > + Master Ending Address #3 = 00FFFFFF > + Master Control #3 = 30 > + Master Enable #4 [Y/N] = N > + Master Starting Address #4 = 00000000 > + Master Ending Address #4 = 00000000 > + Master Address Translation Address #4 = 00000000 > + Master Address Translation Select #4 = 00000000 > + Master Control #4 = 00 > + Short I/O (VMEbus A16) Enable [Y/N] = Y > + Short I/O (VMEbus A16) Control = 01 > + F-Page (VMEbus A24) Enable [Y/N] = Y > + F-Page (VMEbus A24) Control = 02 > + ROM Speed Bank A Code = 05 > + ROM Speed Bank B Code = 05 > + Static RAM Speed Code = 01 > + PCC2 Vector Base = 05 > + VMEC2 Vector Base #1 = 06 > + VMEC2 Vector Base #2 = 07 > + VMEC2 GCSR Group Base Address = CC > + VMEC2 GCSR Board Base Address = 00 > + VMEbus Global Time Out Code = 01 > + Local Bus Time Out Code = 00 > + VMEbus Access Time Out Code = 02 > + > +The NIOT command goes something like this: > + > +.. code-block:: none > + > + 167-Bug>niot > + Controller LUN =00 > + Device LUN =00 > + Node Control Memory Address =FFE10000 > + Client IP Address =0.0.0.0 > + Server IP Address =0.0.0.0 > + Subnet IP Address Mask =255.255.255.0 > + Broadcast IP Address =255.255.255.255 > + Gateway IP Address =0.0.0.0 > + Boot File Name ("NULL" for None) = > + Argument File Name ("NULL" for None) = > + Boot File Load Address =00800000 > + Boot File Execution Address =00800000 > + Boot File Execution Delay =00000000 > + Boot File Length =00000000 > + Boot File Byte Offset =00000000 > + BOOTP/RARP Request Retry =00 > + TFTP/ARP Request Retry =00 > + Trace Character Buffer Address =00000000 > + BOOTP/RARP Request Control: Always/When-Needed (A/W)=A > + BOOTP/RARP Reply Update Control: Yes/No (Y/N) =N > + > +References > +---------- > + > +* `User Manual < > https://prep.fnal.gov/catalog/hardware_info/motorola/mvme167_d3.pdf>`_ > > uC5282 > ====== > > -TODO. > +Overview > +-------- > + > +The uC5282 is a compact, embedded microprocessor module ideal for > networked > +control and communication applications. The device is available in a > standard > +144pin soDIMM edge connector format to allow fast integration into > products. > +The module is based on the Freescale ColdFire MCF5282 microprocessor and > +includes all required system memory and physical terminations to enable > most > +applications without the need for external circuitry. The uC5282 features > +Ethernet, CAN and serial communications systems as well as standard > peripheral > +device connectivity using I2C, QSPI or data/address logic. > + > +References > +---------- > + > +* `User Manual < > https://prep.fnal.gov/catalog/hardware_info/motorola/mvme167_d3.pdf>`_ > + > -- > 2.17.1 > >
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