This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT. --- bsps/aarch64/shared/start/linkcmds.base | 4 -- bsps/aarch64/shared/start/start.S | 16 +++++ spec/build/bsps/aarch64/a53/abi.yml | 7 +- .../bsps/aarch64/a53/bspa53ilp32qemu.yml | 70 +++++++++++++++++++ .../build/bsps/aarch64/a53/bspa53lp64qemu.yml | 2 +- .../build/bsps/aarch64/a53/linkcmds_ilp32.yml | 68 ++++++++++++++++++ .../a53/{linkcmds.yml => linkcmds_lp64.yml} | 3 + 7 files changed, 164 insertions(+), 6 deletions(-) create mode 100644 spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml rename spec/build/bsps/aarch64/a53/{linkcmds.yml => linkcmds_lp64.yml} (97%)
diff --git a/bsps/aarch64/shared/start/linkcmds.base b/bsps/aarch64/shared/start/linkcmds.base index ff8b379fa7..3da707e627 100644 --- a/bsps/aarch64/shared/start/linkcmds.base +++ b/bsps/aarch64/shared/start/linkcmds.base @@ -34,10 +34,6 @@ * POSSIBILITY OF SUCH DAMAGE. */ -OUTPUT_FORMAT ("elf64-littleaarch64") - -OUTPUT_ARCH (aarch64) - ENTRY (_start) STARTUP (start.o) diff --git a/bsps/aarch64/shared/start/start.S b/bsps/aarch64/shared/start/start.S index d152aaa57f..2a665a4116 100644 --- a/bsps/aarch64/shared/start/start.S +++ b/bsps/aarch64/shared/start/start.S @@ -99,19 +99,31 @@ _start: * Get current per-CPU control and store it in PL1 only Thread ID * Register (TPIDRPRW). */ +#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 + ldr w1, =_Per_CPU_Information +#else ldr x1, =_Per_CPU_Information +#endif add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2 mcr p15, 0, x1, c13, c0, 4 #endif /* Calculate interrupt stack area end for current processor */ +#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 + ldr w1, =_ISR_Stack_size +#else ldr x1, =_ISR_Stack_size +#endif #ifdef RTEMS_SMP add x3, x7, #1 mul x1, x1, x3 #endif +#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 + ldr w2, =_ISR_Stack_area_begin +#else ldr x2, =_ISR_Stack_area_begin +#endif add x3, x1, x2 /* Save original DAIF value */ @@ -133,7 +145,11 @@ _start: * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1 * Exception operation (synchronous errors, IRQ, FIQ, System Errors) uses SP0 */ +#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 + ldr w1, =bsp_stack_exception_size +#else ldr x1, =bsp_stack_exception_size +#endif /* Switch to SP0 and set exception stack */ msr spsel, #0 mov sp, x3 diff --git a/spec/build/bsps/aarch64/a53/abi.yml b/spec/build/bsps/aarch64/a53/abi.yml index f744a14464..745045382c 100644 --- a/spec/build/bsps/aarch64/a53/abi.yml +++ b/spec/build/bsps/aarch64/a53/abi.yml @@ -5,7 +5,12 @@ actions: build-type: option default: - -mcpu=cortex-a53 -default-by-variant: [] +default-by-variant: +- value: + - -mcpu=cortex-a53 + - -mabi=ilp32 + variants: + - aarch64/a53_ilp32_qemu enabled-by: true links: [] name: ABI_FLAGS diff --git a/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml new file mode 100644 index 0000000000..88c9cf948f --- /dev/null +++ b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml @@ -0,0 +1,70 @@ +arch: aarch64 +bsp: a53_ilp32_qemu +build-type: bsp +cflags: [] +cppflags: [] +enabled-by: true +family: a53 +includes: [] +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/aarch64/a53/include/bsp.h + - bsps/aarch64/a53/include/tm27.h +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/aarch64/a53/include/bsp/irq.h + - bsps/include/bsp/arm-gic-irq.h + - bsps/include/bsp/arm-gic-regs.h + - bsps/include/bsp/arm-gic-tm27.h + - bsps/include/bsp/arm-gic.h + - bsps/aarch64/include/bsp/irq-arch.h + - bsps/include/bsp/clock-arm-generic-timer.h +links: +- role: build-dependency + uid: ../start +- role: build-dependency + uid: abi +- role: build-dependency + uid: optloadoff +- role: build-dependency + uid: optnocachelen +- role: build-dependency + uid: optramlen +- role: build-dependency + uid: optramori +- role: build-dependency + uid: tsta53 +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: ../../optcachedata +- role: build-dependency + uid: ../../optcacheinst +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: linkcmds_ilp32 +- role: build-dependency + uid: ../../bspopts +source: +- bsps/aarch64/shared/cache/cache.c +- bsps/aarch64/a53/console/console.c +- bsps/aarch64/a53/start/bspstart.c +- bsps/aarch64/a53/start/bspstarthooks.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/serial/console-termios-init.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/bspgetworkarea-default.c +- bsps/shared/start/bspreset-psci.c +- bsps/shared/start/sbrk.c +- bsps/shared/irq/irq-arm-gicv3.c +- bsps/shared/irq/irq-default-handler.c +- bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/clock/clock-arm-generic-timer.c +- bsps/aarch64/shared/clock/clock-arm-generic-timer-aarch64.c +type: build diff --git a/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml b/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml index 06c3a91265..ee99200b18 100644 --- a/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml +++ b/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml @@ -46,7 +46,7 @@ links: - role: build-dependency uid: ../../opto2 - role: build-dependency - uid: linkcmds + uid: linkcmds_lp64 - role: build-dependency uid: ../../bspopts source: diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml new file mode 100644 index 0000000000..9f6872215a --- /dev/null +++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml @@ -0,0 +1,68 @@ +build-type: config-file +content: | + /* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) + * Written by Kinsey Moore <kinsey.mo...@oarcorp.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + MEMORY { + RAM : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_LOAD_OFFSET}, LENGTH = ${BSP_A53_RAM_LENGTH} - ${BSP_A53_LOAD_OFFSET} - ${BSP_A53_NOCACHE_LENGTH} + NOCACHE : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_RAM_LENGTH} - ${BSP_A53_NOCACHE_LENGTH}, LENGTH = ${BSP_A53_NOCACHE_LENGTH} + } + + REGION_ALIAS ("REGION_START", RAM); + REGION_ALIAS ("REGION_VECTOR", RAM); + REGION_ALIAS ("REGION_TEXT", RAM); + REGION_ALIAS ("REGION_TEXT_LOAD", RAM); + REGION_ALIAS ("REGION_RODATA", RAM); + REGION_ALIAS ("REGION_RODATA_LOAD", RAM); + REGION_ALIAS ("REGION_DATA", RAM); + REGION_ALIAS ("REGION_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_FAST_TEXT", RAM); + REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM); + REGION_ALIAS ("REGION_FAST_DATA", RAM); + REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_BSS", RAM); + REGION_ALIAS ("REGION_WORK", RAM); + REGION_ALIAS ("REGION_STACK", RAM); + REGION_ALIAS ("REGION_NOCACHE", NOCACHE); + REGION_ALIAS ("REGION_NOCACHE_LOAD", NOCACHE); + + bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? bsp_stack_exception_size : 1024; + + bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M; + + bsp_vector_table_in_start_section = 1; + + OUTPUT_FORMAT ("elf32-littleaarch64") + OUTPUT_ARCH (aarch64:ilp32) + + INCLUDE linkcmds.base +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds +type: build diff --git a/spec/build/bsps/aarch64/a53/linkcmds.yml b/spec/build/bsps/aarch64/a53/linkcmds_lp64.yml similarity index 97% rename from spec/build/bsps/aarch64/a53/linkcmds.yml rename to spec/build/bsps/aarch64/a53/linkcmds_lp64.yml index 23c99f693a..33732a7fbb 100644 --- a/spec/build/bsps/aarch64/a53/linkcmds.yml +++ b/spec/build/bsps/aarch64/a53/linkcmds_lp64.yml @@ -57,6 +57,9 @@ content: | bsp_vector_table_in_start_section = 1; + OUTPUT_FORMAT ("elf64-littleaarch64") + OUTPUT_ARCH (aarch64) + INCLUDE linkcmds.base enabled-by: true install-path: ${BSP_LIBDIR} -- 2.20.1 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel