On 7/1/2021 14:10, Gedare Bloom wrote:
On Thu, Jul 1, 2021 at 12:28 PM Kinsey Moore <kinsey.mo...@oarcorp.com> wrote:
Update the ZynqMP documentation for the new hardware BSP variants
including information about booting, boot image generation, and
networking.
---
user/bsps/aarch64/xilinx-zynqmp.rst | 56 ++++++++++++++++++++++++-----
1 file changed, 48 insertions(+), 8 deletions(-)
diff --git a/user/bsps/aarch64/xilinx-zynqmp.rst
b/user/bsps/aarch64/xilinx-zynqmp.rst
index 7401e84..333ce8e 100644
--- a/user/bsps/aarch64/xilinx-zynqmp.rst
+++ b/user/bsps/aarch64/xilinx-zynqmp.rst
@@ -4,19 +4,45 @@
.. _BSP_aarch64_qemu_xilinx_zynqmp_ilp32_qemu:
.. _BSP_aarch64_qemu_xilinx_zynqmp_lp64_qemu:
+.. _BSP_aarch64_qemu_xilinx_zynqmp_ilp32_zu3eg:
+.. _BSP_aarch64_qemu_xilinx_zynqmp_lp64_zu3eg:
Qemu Xilinx ZynqMP
==================
-This BSP supports two variants, `xilinx-zynqmp-ilp32-qemu` and
-`xilinx-zynqmp-lp64-qemu`. The basic hardware initialization is performed by
the
-BSP. These BSPs support the GICv2 interrupt controller present in all ZynqMP
-systems.
+This BSP supports four variants: `xilinx-zynqmp-ilp32-qemu`,
+`xilinx-zynqmp-lp64-qemu`, `xilinx-zynqmp-ilp32-zu3eg`, and
+`xilinx-zynqmp-lp64-zu3eg`. The basic hardware initialization is performed by
This is a little confusing because there needs to be some hw
initialization first (e.g., by u-boot or ATF). Maybe clarify that
point. Otherwise, thanks for the addition looks great.
Thanks, I'll tweak that wording before commit.
Kinsey
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