The MicroBlaze Machine Status Register (MSR) does not have a flag that
designates the current execution status of the interrupt handler other
than the Interrupt Enable (IE) bit which may be unset for other reasons.
This makes use of R13 to signal the current interrupt nesting
encompassing the entirety of interrupt execution versus the more limited
scope of ISR_NEST_LEVEL. R13 would typically be used as a TLS data
pointer, but is currently unused by RTEMS. This interrupt flag is
necessary for a pure software break libdebugger backend implementation
since interrupt execution status must be known during thread dispatch.
---
cpukit/score/cpu/microblaze/cpu_asm.S | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 6bd81eedd9..5bb1a944b0 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -41,6 +41,17 @@
.align 2
_ISR_Handler:
+ /*
+ * Increment interrupt context flag. This TLS register is coopted for
+ * this purpose since it is not used by RTEMS. R2 would suffice as well,
+ * but would need to be added to Context_Control. This is used by
+ * libdebugger since ISR_NEST_LEVEL is not sufficient to indicate
+ * execution in interrupt context after the stack is switched back for
+ * thread dispatch. There is no MSR bit to indicate Interrupt in
+ * Progress.
+ */
+ addik r13, r13, 1
+
/* Save stack frame */
swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
@@ -153,5 +164,8 @@ quick_exit:
/* Remove stack frame */
addik r1, r1, CPU_INTERRUPT_FRAME_SIZE
+ /* Decrement interrupt context flag */
+ addik r13, r13, -1
+
rtid r14, 0
nop
--
2.30.2
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