This may also be an issue for ARM, RISC-V and others as it doesn't
appear that ARM saves CPSR during context switch and I couldn't tell
that RISC-V does this either, though I'm less familiar with it.
Kinsey
On 2/25/2022 17:33, Kinsey Moore wrote:
If a task migrates to a newly turned-up CPU as the first task it
executes, no guarantees are made about whether interrupts are enabled
and it is possible for a task to change interrupt enable states during
the migration. This preserves interrupt state across context switches.
---
cpukit/score/cpu/aarch64/cpu_asm.S | 4 ++++
cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 7 ++++---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/cpukit/score/cpu/aarch64/cpu_asm.S
b/cpukit/score/cpu/aarch64/cpu_asm.S
index 2379698336..4234b428aa 100644
--- a/cpukit/score/cpu/aarch64/cpu_asm.S
+++ b/cpukit/score/cpu/aarch64/cpu_asm.S
@@ -83,6 +83,8 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
stp fp, lr, [x0, #0x50]
mov x4, sp
str x4, [x0, #0x60]
+ mrs x5, daif
+ str x5, [x0, #0x78]
#ifdef AARCH64_MULTILIB_VFP
add x5, x0, #AARCH64_CONTEXT_CONTROL_D8_OFFSET
@@ -151,6 +153,8 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
ldp fp, lr, [x1, #0x50]
ldr x4, [x1, #0x60]
mov sp, x4
+ ldr x5, [x1, #0x78]
+ msr daif, x5
ret
/*
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index e1d9f0a5c2..2f252bf2f4 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -127,16 +127,16 @@
#define AARCH64_CONTEXT_CONTROL_THREAD_ID_OFFSET 0x70
#ifdef AARCH64_MULTILIB_VFP
- #define AARCH64_CONTEXT_CONTROL_D8_OFFSET 0x78
+ #define AARCH64_CONTEXT_CONTROL_D8_OFFSET 0x80
#endif
#define AARCH64_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 0x68
#ifdef RTEMS_SMP
#if defined(AARCH64_MULTILIB_VFP)
- #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0xb8
+ #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0xc0
#else
- #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x78
+ #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x80
#endif
#endif
@@ -174,6 +174,7 @@ typedef struct {
uint64_t register_sp;
uint64_t isr_dispatch_disable;
uint64_t thread_id;
+ uint64_t daif;
#ifdef AARCH64_MULTILIB_VFP
uint64_t register_d8;
uint64_t register_d9;
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