From: Martin Aberg <mab...@gaisler.com> Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV
Compatible with the following NOEL-V FPGA example design ranges available from Cobham Gaisler. Follow the links for free bit-streams, DTS/DTB, user's manuals and quick-start guides: - NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7) - NOEL-PF-EX (https://www.gaisler.com/NOEL-PF) - NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU) Uses the shared GRLIB APBUART console driver "apbuart_termios.c". APBUART devices are probed using device tree. Update #4225. --- bsps/riscv/noel/console/console-config.c | 209 ++++++++++++++++++ bsps/riscv/noel/include/bsp.h | 76 +++++++ bsps/riscv/noel/include/bsp/irq.h | 75 +++++++ bsps/riscv/noel/include/tm27.h | 1 + bsps/riscv/noel/start/bsp_fatal_halt.c | 46 ++++ bsps/riscv/riscv/include/bsp.h | 2 + bsps/riscv/riscv/include/bsp/irq.h | 2 + spec/build/bsps/riscv/noel/abi.yml | 48 ++++ spec/build/bsps/riscv/noel/bspnoel32im.yml | 19 ++ spec/build/bsps/riscv/noel/bspnoel32imafd.yml | 19 ++ spec/build/bsps/riscv/noel/bspnoel64imac.yml | 19 ++ spec/build/bsps/riscv/noel/bspnoel64imafd.yml | 19 ++ .../build/bsps/riscv/noel/bspnoel64imafdc.yml | 19 ++ spec/build/bsps/riscv/noel/grp.yml | 59 +++++ spec/build/bsps/riscv/noel/obj.yml | 38 ++++ spec/build/bsps/riscv/noel/objsmp.yml | 15 ++ spec/build/bsps/riscv/noel/optconirq.yml | 16 ++ spec/build/bsps/riscv/noel/optextirqmax.yml | 16 ++ spec/build/bsps/riscv/optrambegin.yml | 3 + spec/build/cpukit/optarchbits.yml | 2 + spec/build/cpukit/optsmp.yml | 4 + 21 files changed, 707 insertions(+) create mode 100644 bsps/riscv/noel/console/console-config.c create mode 100644 bsps/riscv/noel/include/bsp.h create mode 100644 bsps/riscv/noel/include/bsp/irq.h create mode 100644 bsps/riscv/noel/include/tm27.h create mode 100644 bsps/riscv/noel/start/bsp_fatal_halt.c create mode 100644 spec/build/bsps/riscv/noel/abi.yml create mode 100644 spec/build/bsps/riscv/noel/bspnoel32im.yml create mode 100644 spec/build/bsps/riscv/noel/bspnoel32imafd.yml create mode 100644 spec/build/bsps/riscv/noel/bspnoel64imac.yml create mode 100644 spec/build/bsps/riscv/noel/bspnoel64imafd.yml create mode 100644 spec/build/bsps/riscv/noel/bspnoel64imafdc.yml create mode 100644 spec/build/bsps/riscv/noel/grp.yml create mode 100644 spec/build/bsps/riscv/noel/obj.yml create mode 100644 spec/build/bsps/riscv/noel/objsmp.yml create mode 100644 spec/build/bsps/riscv/noel/optconirq.yml create mode 100644 spec/build/bsps/riscv/noel/optextirqmax.yml diff --git a/bsps/riscv/noel/console/console-config.c b/bsps/riscv/noel/console/console-config.c new file mode 100644 index 0000000000..eff3b75250 --- /dev/null +++ b/bsps/riscv/noel/console/console-config.c @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsRISCVNOEL + * + * @brief This source file contains NOEL-V/APBUART definitions of + * ::BSP_output_char_function_type and :: BSP_output_char and an + * implementation of console_initialize(). + */ + +/* + * Copyright (c) 2021 Cobham Gaisler AB. + * + * Copyright (C) 2018 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/bspIo.h> +#include <rtems/console.h> +#include <rtems/sysinit.h> +#include <rtems/termiostypes.h> + +#include <bsp/fatal.h> +#include <bsp/fdt.h> +#include <bsp/irq.h> +#include <bsp/riscv.h> + +#include <libfdt.h> + +#define RISCV_CONSOLE_MAX_APBUART_DEVICES 4 + +#include <grlib/apbuart.h> +#include <grlib/apbuart_termios.h> +static struct apbuart_context apbuarts[RISCV_CONSOLE_MAX_APBUART_DEVICES]; +static size_t apbuart_devices = 0; + +static struct { + rtems_termios_device_context *context; + void (*putchar)(rtems_termios_device_context *base, char c); + int (*getchar)(rtems_termios_device_context *base); +} riscv_console; + +static void riscv_output_char(char c) +{ + (*riscv_console.putchar)(riscv_console.context, c); +} + +static void apbuart_putchar(rtems_termios_device_context *base, char c) +{ + struct apbuart_context *ctx = (struct apbuart_context *) base; + apbuart_outbyte_polled(ctx->regs, c); +} + +static int apbuart_getchar(rtems_termios_device_context *base) +{ + struct apbuart_context *ctx = (struct apbuart_context *) base; + return apbuart_inbyte_nonblocking(ctx->regs); +} + +#define RISCV_CONSOLE_IS_COMPATIBLE(actual, actual_len, desired) \ + (actual_len == sizeof(desired) \ + && memcmp(actual, desired, sizeof(desired) - 1) == 0) + +static uint32_t get_core_frequency(void) +{ + uint32_t node; + const char *fdt; + int len; + const fdt32_t *val; + + fdt = bsp_fdt_get(); + node = fdt_node_offset_by_compatible(fdt, -1, "fixed-clock"); + + val = fdt_getprop(fdt, node, "clock-frequency", &len); + if (val != NULL && len == 4) { + return fdt32_to_cpu(*val); + } + return 0; +} + +static void riscv_console_probe(void) +{ + const void *fdt; + int node; + + fdt = bsp_fdt_get(); + + node = fdt_next_node(fdt, -1, NULL); + + while (node >= 0) { + const char *compat; + int compat_len; + + compat = fdt_getprop(fdt, node, "compatible", &compat_len); + if (compat == NULL) { + compat_len = 0; + } + + if ( + RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "gaisler,apbuart") + && (apbuart_devices < RISCV_CONSOLE_MAX_APBUART_DEVICES) + ) { + struct apbuart_context *ctx; + fdt32_t *val; + int len; + + ctx = &apbuarts[apbuart_devices]; + + ctx->regs = riscv_fdt_get_address(fdt, node); + if (ctx->regs == NULL) { + bsp_fatal(RISCV_FATAL_NO_NS16550_REG_IN_DEVICE_TREE); + } + + ctx->freq_hz = get_core_frequency(); + + val = (fdt32_t *) fdt_getprop(fdt, node, "interrupts", &len); + if (val == NULL || len != 4) { + bsp_fatal(RISCV_FATAL_NO_NS16550_INTERRUPTS_IN_DEVICE_TREE); + } + ctx->irq = RISCV_INTERRUPT_VECTOR_EXTERNAL(fdt32_to_cpu(val[0])); + + if (apbuart_devices == 0) { + riscv_console.context = &ctx->base; + riscv_console.putchar = apbuart_putchar; + riscv_console.getchar = apbuart_getchar; + } + + rtems_termios_device_context_initialize(&ctx->base, "APBUART"); + + apbuart_devices++; + }; + + node = fdt_next_node(fdt, node, NULL); + } + + BSP_output_char = riscv_output_char; +} + +static void riscv_output_char_init(char c) +{ + riscv_console_probe(); + riscv_output_char(c); +} + +BSP_output_char_function_type BSP_output_char = riscv_output_char_init; + +BSP_polling_getchar_function_type BSP_poll_char = NULL; + +rtems_status_code console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + char path[] = "/dev/ttyS?"; + + rtems_termios_initialize(); + + const rtems_termios_device_handler *handler = &apbuart_handler_polled; + + if (CONSOLE_USE_INTERRUPTS) { + handler = &apbuart_handler_interrupt; + } + for (size_t i = 0; i < apbuart_devices; ++i) { + struct apbuart_context *ctx; + + ctx = &apbuarts[i]; + path[sizeof(path) - 2] = (char) ('0' + i); + rtems_termios_device_install(path, handler, NULL, &ctx->base); + + if (&ctx->base == riscv_console.context) { + link(path, CONSOLE_DEVICE_NAME); + } + } + + return RTEMS_SUCCESSFUL; +} + +RTEMS_SYSINIT_ITEM( + riscv_console_probe, + RTEMS_SYSINIT_BSP_START, + RTEMS_SYSINIT_ORDER_LAST_BUT_5 +); diff --git a/bsps/riscv/noel/include/bsp.h b/bsps/riscv/noel/include/bsp.h new file mode 100644 index 0000000000..1b6686a01a --- /dev/null +++ b/bsps/riscv/noel/include/bsp.h @@ -0,0 +1,76 @@ +/** + * @file + * + * @ingroup RTEMSBSPsRISCVNOEL + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2021 Cobham Gaisler AB. + * + * Copyright (c) 2015 University of York. + * Hesham Almatary <hes...@alumni.york.ac.uk> + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_RISCV_NOEL_H +#define LIBBSP_RISCV_NOEL_H + +/** + * @defgroup RTEMSBSPsRISCVNOEL NOEL-V + * + * @ingroup RTEMSBSPsRISCV + * + * @brief NOEL-V RISC-V Board Support Package. + * + * @{ + */ + +#include <rtems.h> +#include <rtems/clockdrv.h> +#include <rtems/console.h> + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems/devnull.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_FDT_IS_SUPPORTED + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* LIBBSP_RISCV_NOEL_H */ diff --git a/bsps/riscv/noel/include/bsp/irq.h b/bsps/riscv/noel/include/bsp/irq.h new file mode 100644 index 0000000000..95cbe554b6 --- /dev/null +++ b/bsps/riscv/noel/include/bsp/irq.h @@ -0,0 +1,75 @@ +/** + * @file + * + * @ingroup RISCV_IRQ + * + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2021 Cobham Gaisler AB. + * + * Copyright (c) 2018 embedded brains GmbH + * + * Copyright (c) 2015 University of York. + * Hesham Almatary <hes...@alumni.york.ac.uk> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_RISCV_NOEL_IRQ_H +#define LIBBSP_RISCV_NOEL_IRQ_H + +#ifndef ASM + +#include <bsp.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> +#include <rtems/score/processormask.h> + +#define RISCV_INTERRUPT_VECTOR_SOFTWARE 0 + +#define RISCV_INTERRUPT_VECTOR_TIMER 1 + +#define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2) + +#define RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2) + +#define RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2) + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS - 1) + +void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +); + +void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +); + +#endif /* ASM */ + +#endif /* LIBBSP_RISCV_NOEL_IRQ_H */ diff --git a/bsps/riscv/noel/include/tm27.h b/bsps/riscv/noel/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/riscv/noel/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/riscv/noel/start/bsp_fatal_halt.c b/bsps/riscv/noel/start/bsp_fatal_halt.c new file mode 100644 index 0000000000..93c4ee42b5 --- /dev/null +++ b/bsps/riscv/noel/start/bsp_fatal_halt.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2021 Cobham Gaisler AB + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp/riscv.h> + +/* From bsps/arm/fvp/include/bsp/semihosting.h */ +#define TARGET_SYS_EXIT_EXTENDED 0x20 +#define ADP_Stopped_ApplicationExit 0x20026 + +void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ) +{ + uint64_t args[2] = {ADP_Stopped_ApplicationExit, error}; + __asm__ volatile ("li a0, %0" ::"i"(TARGET_SYS_EXIT_EXTENDED)); + __asm__ volatile ("mv a1, %0" ::"r"(&args)); + __asm__ volatile ("slli zero, zero, 0x1f"); + __asm__ volatile ("ebreak"); + __asm__ volatile ("srai zero, zero, 0x7"); + + while (true) { + ; + } +} diff --git a/bsps/riscv/riscv/include/bsp.h b/bsps/riscv/riscv/include/bsp.h index d19f0d03a5..911b85f4a3 100644 --- a/bsps/riscv/riscv/include/bsp.h +++ b/bsps/riscv/riscv/include/bsp.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * diff --git a/bsps/riscv/riscv/include/bsp/irq.h b/bsps/riscv/riscv/include/bsp/irq.h index 1b67c4e046..ae1ba3c757 100644 --- a/bsps/riscv/riscv/include/bsp/irq.h +++ b/bsps/riscv/riscv/include/bsp/irq.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * diff --git a/spec/build/bsps/riscv/noel/abi.yml b/spec/build/bsps/riscv/noel/abi.yml new file mode 100644 index 0000000000..f81e0c1a60 --- /dev/null +++ b/spec/build/bsps/riscv/noel/abi.yml @@ -0,0 +1,48 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- split: null +- env-append: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: +- -march=rv32ima +- -mabi=ilp32 +default-by-variant: +- value: + - -march=rv64imafdc + - -mabi=lp64d + variants: + - riscv/noel64imafdc +- value: + - -march=rv64imafd + - -mabi=lp64d + variants: + - riscv/noel64imafd +- value: + - -march=rv64imac + - -mabi=lp64 + variants: + - riscv/noel64imac +- value: + - -march=rv64im + - -mabi=lp64 + variants: + - riscv/noel64im +- value: + - -march=rv32imafd + - -mabi=ilp32d + variants: + - riscv/noel32imafd +- value: + - -march=rv32im + - -mabi=ilp32 + variants: + - riscv/noel32im +description: | + ABI flags +enabled-by: true +links: [] +name: ABI_FLAGS +type: build diff --git a/spec/build/bsps/riscv/noel/bspnoel32im.yml b/spec/build/bsps/riscv/noel/bspnoel32im.yml new file mode 100644 index 0000000000..bcb27a5750 --- /dev/null +++ b/spec/build/bsps/riscv/noel/bspnoel32im.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: riscv +bsp: noel32im +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +enabled-by: true +family: riscv +includes: [] +install: [] +links: +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: grp +source: [] +type: build diff --git a/spec/build/bsps/riscv/noel/bspnoel32imafd.yml b/spec/build/bsps/riscv/noel/bspnoel32imafd.yml new file mode 100644 index 0000000000..e105620c74 --- /dev/null +++ b/spec/build/bsps/riscv/noel/bspnoel32imafd.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: riscv +bsp: noel32imafd +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +enabled-by: true +family: riscv +includes: [] +install: [] +links: +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: grp +source: [] +type: build diff --git a/spec/build/bsps/riscv/noel/bspnoel64imac.yml b/spec/build/bsps/riscv/noel/bspnoel64imac.yml new file mode 100644 index 0000000000..e32bdb3322 --- /dev/null +++ b/spec/build/bsps/riscv/noel/bspnoel64imac.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: riscv +bsp: noel64imac +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +enabled-by: true +family: riscv +includes: [] +install: [] +links: +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: grp +source: [] +type: build diff --git a/spec/build/bsps/riscv/noel/bspnoel64imafd.yml b/spec/build/bsps/riscv/noel/bspnoel64imafd.yml new file mode 100644 index 0000000000..ca9f54df0a --- /dev/null +++ b/spec/build/bsps/riscv/noel/bspnoel64imafd.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: riscv +bsp: noel64imafd +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +enabled-by: true +family: riscv +includes: [] +install: [] +links: +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: grp +source: [] +type: build diff --git a/spec/build/bsps/riscv/noel/bspnoel64imafdc.yml b/spec/build/bsps/riscv/noel/bspnoel64imafdc.yml new file mode 100644 index 0000000000..cfde93714c --- /dev/null +++ b/spec/build/bsps/riscv/noel/bspnoel64imafdc.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: riscv +bsp: noel64imafdc +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +enabled-by: true +family: riscv +includes: [] +install: [] +links: +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: grp +source: [] +type: build diff --git a/spec/build/bsps/riscv/noel/grp.yml b/spec/build/bsps/riscv/noel/grp.yml new file mode 100644 index 0000000000..b4ad824b30 --- /dev/null +++ b/spec/build/bsps/riscv/noel/grp.yml @@ -0,0 +1,59 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: group +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: [] +ldflags: [] +links: +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: ../../optclang +- role: build-dependency + uid: ../../optconsolebaud +- role: build-dependency + uid: ../../optgcc +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../optrambegin +- role: build-dependency + uid: ../optramsize +- role: build-dependency + uid: abi +- role: build-dependency + uid: obj +- role: build-dependency + uid: objsmp +- role: build-dependency + uid: ../../objmem +- role: build-dependency + uid: optextirqmax +- role: build-dependency + uid: ../../optfdtcpyro +- role: build-dependency + uid: ../../optfdtmxsz +- role: build-dependency + uid: ../../optfdtro +- role: build-dependency + uid: ../../optfdtuboot +- role: build-dependency + uid: optconirq +- role: build-dependency + uid: ../linkcmds +- role: build-dependency + uid: ../linkcmdsbase +- role: build-dependency + uid: ../start +- role: build-dependency + uid: ../../bspopts +type: build +use-after: [] +use-before: [] diff --git a/spec/build/bsps/riscv/noel/obj.yml b/spec/build/bsps/riscv/noel/obj.yml new file mode 100644 index 0000000000..8e7682f2b0 --- /dev/null +++ b/spec/build/bsps/riscv/noel/obj.yml @@ -0,0 +1,38 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/riscv/noel/include/bsp.h + - bsps/riscv/noel/include/tm27.h +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/riscv/noel/include/bsp/irq.h + - bsps/riscv/riscv/include/bsp/riscv.h +links: [] +source: +- bsps/riscv/riscv/clock/clockdrv.c +- bsps/riscv/noel/console/console-config.c +- bsps/riscv/riscv/irq/irq.c +- bsps/riscv/noel/start/bsp_fatal_halt.c +- bsps/riscv/riscv/start/bspstart.c +- bsps/shared/cache/nocache.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/irq/irq-default-handler.c +- bsps/shared/start/bsp-fdt.c +- bsps/shared/start/bspfatal-default.c +- bsps/riscv/shared/start/bspgetworkarea-fromstack.c +- bsps/shared/start/bspreset-empty.c +- bsps/shared/start/gettargethash-default.c +- bsps/shared/grlib/uart/apbuart_polled.c +- bsps/shared/grlib/uart/apbuart_termios.c +type: build diff --git a/spec/build/bsps/riscv/noel/objsmp.yml b/spec/build/bsps/riscv/noel/objsmp.yml new file mode 100644 index 0000000000..46369f977e --- /dev/null +++ b/spec/build/bsps/riscv/noel/objsmp.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +cxxflags: [] +enabled-by: +- RTEMS_SMP +includes: [] +install: [] +links: [] +source: +- bsps/riscv/riscv/start/bspsmp.c +type: build diff --git a/spec/build/bsps/riscv/noel/optconirq.yml b/spec/build/bsps/riscv/noel/optconirq.yml new file mode 100644 index 0000000000..d836822efb --- /dev/null +++ b/spec/build/bsps/riscv/noel/optconirq.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 0 +default-by-variant: [] +description: | + The APBUART console driver can operate in either polled or interrupt mode. +enabled-by: true +format: '{}' +links: [] +name: CONSOLE_USE_INTERRUPTS +type: build diff --git a/spec/build/bsps/riscv/noel/optextirqmax.yml b/spec/build/bsps/riscv/noel/optextirqmax.yml new file mode 100644 index 0000000000..ffa84748b6 --- /dev/null +++ b/spec/build/bsps/riscv/noel/optextirqmax.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 64 +default-by-variant: [] +description: | + maximum number of external interrupts supported by the BSP (default 64) +enabled-by: true +format: '{}' +links: [] +name: RISCV_MAXIMUM_EXTERNAL_INTERRUPTS +type: build diff --git a/spec/build/bsps/riscv/optrambegin.yml b/spec/build/bsps/riscv/optrambegin.yml index 2073926dac..4a867a1921 100644 --- a/spec/build/bsps/riscv/optrambegin.yml +++ b/spec/build/bsps/riscv/optrambegin.yml @@ -16,6 +16,9 @@ default-by-variant: - value: 1879048192 variants: - riscv/rv64.* +- value: 0 + variants: + - riscv/noel.* - value: 1073741824 variants: - riscv/griscv diff --git a/spec/build/cpukit/optarchbits.yml b/spec/build/cpukit/optarchbits.yml index ac9a1f19cd..f7b652cc60 100644 --- a/spec/build/cpukit/optarchbits.yml +++ b/spec/build/cpukit/optarchbits.yml @@ -11,11 +11,13 @@ default-by-variant: - value: - '64' variants: + - riscv/noel64.* - riscv/rv64.* - value: - '32' variants: - riscv/griscv + - riscv/noel32.* - riscv/rv32.* description: The architecture word bits for the clang target triple. enabled-by: diff --git a/spec/build/cpukit/optsmp.yml b/spec/build/cpukit/optsmp.yml index b4a2d2c771..a9e62bf8b9 100644 --- a/spec/build/cpukit/optsmp.yml +++ b/spec/build/cpukit/optsmp.yml @@ -31,6 +31,10 @@ enabled-by: - riscv/griscv - riscv/grv32imac - riscv/grv32imafdc +- riscv/noel32imafd +- riscv/noel64imac +- riscv/noel64imafdc +- riscv/noel64imafd - riscv/rv32iac - riscv/rv32imac - riscv/rv32imafc -- 2.34.1 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