I agree – I am working on a riscv BSP variant (Sipeed MAIX Bit with K210 CPU) where the RTEMS image can be flashed directly to the board and boots without a bootloader. I was also wondering if the statement “Each variant corresponds to a GCC multilib” is still accurate as BSP variants such as the FE310Arty and Microchip Polarfire are added? Thanks, Alan From: heshamelmat...@gmail.com From: Hesham Almatary <hesham.almat...@cl.cam.ac.uk> The BSP is capable of initialising the hardware being the first software that takes control on hardware reset (after the bootrom). For instance, using on QEMU's virt platforms, RTEMS runs as a bios without BBL. Similarily, RTEMS can also be run on harware/FPGA and loaded using GDB; the bootrom (or a GDB script) should just set the a0/a1 registers with the boot HART ID and DTB address respectively. --- user/bsps/bsps-riscv.rst | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst index 48e7ee7..224506d 100644 --- a/user/bsps/bsps-riscv.rst +++ b/user/bsps/bsps-riscv.rst @@ -43,9 +43,7 @@ This BSP offers 15 variants: Each variant corresponds to a GCC multilib. A particular variant reflects an ISA with ABI and code model choice.
-The basic hardware initialization is not performed by the BSP. A boot loader -with device tree support must be used to start the BSP, e.g. BBL. The BSP must -be started im machine mode. +The BSP must be started im machine mode.
The reference platform for this BSP is the Qemu `virt` machine.
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