This adds a BSP variant for the ZynqMP BSP family to support the Innoflight CFC-400X platform. --- bsps/aarch64/xilinx-zynqmp/console/console.c | 72 +++++++++++++++++++ bsps/aarch64/xilinx-zynqmp/include/bsp.h | 11 +++ .../aarch64/xilinx-zynqmp/start/bspstartmmu.c | 7 ++ .../aarch64/xilinx-zynqmp/bspcfc400xlp64.yml | 21 ++++++ .../bsps/aarch64/xilinx-zynqmp/optloadoff.yml | 1 + .../aarch64/xilinx-zynqmp/optmgmtbase.yml | 20 ++++++ .../bsps/aarch64/xilinx-zynqmp/optramori.yml | 1 + spec/build/cpukit/optsmp.yml | 1 + 8 files changed, 134 insertions(+) create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/bspcfc400xlp64.yml create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optmgmtbase.yml
diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c b/bsps/aarch64/xilinx-zynqmp/console/console.c index d1948f1a0c..2fe71787dd 100644 --- a/bsps/aarch64/xilinx-zynqmp/console/console.c +++ b/bsps/aarch64/xilinx-zynqmp/console/console.c @@ -43,6 +43,69 @@ #include <bspopts.h> +#ifdef BSP_XILINX_ZYNQMP_MGMT_UART_BASE +#include <libchip/ns16550.h> + +/* These values come from the super_if_axi_uart16550_0 DTS entry */ +/* From the Linux DTS, reg-offset */ +#define MGMT_PORT_OFFSET 0x1000 +/* From the Linux DTS, 89 + 32 (Shared Peripheral Interrupt offset) */ +#define MGMT_PORT_IRQ 121 +/* This provides a clock divider of 14 */ +#define MGMT_PORT_CLK 25804800 + +static uint8_t get_register(uintptr_t addr, uint8_t i) +{ + volatile uint8_t *reg = (uint8_t *) addr; + + i <<= 2; + return reg [i]; +} + +static void set_register(uintptr_t addr, uint8_t i, uint8_t val) +{ + volatile uint8_t *reg = (uint8_t *) addr; + + i <<= 2; + reg [i] = val; +} + +static ns16550_context zynqmp_mgmt_uart_context_0 = { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("Management UART 0"), + .get_reg = get_register, + .set_reg = set_register, + .port = BSP_XILINX_ZYNQMP_MGMT_UART_BASE + MGMT_PORT_OFFSET, + .irq = MGMT_PORT_IRQ, + .clock = MGMT_PORT_CLK, + .initial_baud = 115200, +}; + +__attribute__ ((weak)) void zynqmp_configure_management_console(void) +{ + /* This SLIP-encoded watchdog command sets timeouts to 0xFFFFFFFF seconds. */ + const char mgmt_watchdog_cmd[] = + "\xc0\xda\x00\x00\xff\xff\xff\xff\xff\x00\xff\xff\xff\xffM#\xc0"; + + /* Send the system watchdog configuration command */ + for (int i = 0; i < sizeof(mgmt_watchdog_cmd); i++) { + ns16550_polled_putchar(&zynqmp_mgmt_uart_context_0.base, mgmt_watchdog_cmd[i]); + } +} + +static void zynqmp_management_console_init(void) +{ + ns16550_probe(&zynqmp_mgmt_uart_context_0.base); + + zynqmp_configure_management_console(); +} + +RTEMS_SYSINIT_ITEM( + zynqmp_management_console_init, + RTEMS_SYSINIT_BSP_START, + RTEMS_SYSINIT_ORDER_FIRST +); +#endif + static zynq_uart_context zynqmp_uart_instances[2] = { { .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ), @@ -81,6 +144,15 @@ rtems_status_code console_initialize( } } +#ifdef BSP_XILINX_ZYNQMP_MGMT_UART_BASE + rtems_termios_device_install( + "/dev/ttyMGMT0", + &ns16550_handler_polled, + NULL, + &zynqmp_mgmt_uart_context_0.base + ); +#endif + return RTEMS_SUCCESSFUL; } diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp.h b/bsps/aarch64/xilinx-zynqmp/include/bsp.h index d937a313f2..c823d963c5 100644 --- a/bsps/aarch64/xilinx-zynqmp/include/bsp.h +++ b/bsps/aarch64/xilinx-zynqmp/include/bsp.h @@ -83,6 +83,17 @@ uint32_t zynqmp_clock_i2c0(void); uint32_t zynqmp_clock_i2c1(void); +#ifdef BSP_XILINX_ZYNQMP_MGMT_UART_BASE +/** + * @brief Zynq UltraScale+ MPSoC specific set up of a management console. + * + * The ZynqMP SoC's programmable logic can provide a serial interface for system + * management which may need special initialization. Provide in the application + * to override the defaults in the BSP. + */ +__attribute__ ((weak)) void zynqmp_configure_management_console(void); +#endif + #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/bsps/aarch64/xilinx-zynqmp/start/bspstartmmu.c b/bsps/aarch64/xilinx-zynqmp/start/bspstartmmu.c index 33ca1eafab..30b926a7c0 100644 --- a/bsps/aarch64/xilinx-zynqmp/start/bspstartmmu.c +++ b/bsps/aarch64/xilinx-zynqmp/start/bspstartmmu.c @@ -50,6 +50,13 @@ zynqmp_mmu_config_table[] = { .begin = 0xfd000000U, .end = 0xffc00000U, .flags = AARCH64_MMU_DEVICE +#ifdef BSP_XILINX_ZYNQMP_MGMT_UART_BASE +/* This covers the range of addresses where the UART could be */ + }, { + .begin = 0x80000000U, + .end = 0x90000000U, + .flags = AARCH64_MMU_DEVICE +#endif } }; diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/bspcfc400xlp64.yml b/spec/build/bsps/aarch64/xilinx-zynqmp/bspcfc400xlp64.yml new file mode 100644 index 0000000000..05e53c3539 --- /dev/null +++ b/spec/build/bsps/aarch64/xilinx-zynqmp/bspcfc400xlp64.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: aarch64 +bsp: xilinx_zynqmp_lp64_cfc400x +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2022 On-Line Applications Research (OAR) +cppflags: [] +enabled-by: true +family: xilinx-zynqmp +includes: [] +install: [] +links: +- role: build-dependency + uid: grp_zu3eg +- role: build-dependency + uid: linkcmds_lp64 +- role: build-dependency + uid: optmgmtbase +source: [] +type: build diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/optloadoff.yml b/spec/build/bsps/aarch64/xilinx-zynqmp/optloadoff.yml index 0bdc2d61df..976a4aeb0e 100644 --- a/spec/build/bsps/aarch64/xilinx-zynqmp/optloadoff.yml +++ b/spec/build/bsps/aarch64/xilinx-zynqmp/optloadoff.yml @@ -11,6 +11,7 @@ default: 32768 default-by-variant: - value: 0x0 variants: + - aarch64/xilinx_zynqmp_lp64_cfc400x - aarch64/xilinx_zynqmp_lp64_zu3eg - aarch64/xilinx_zynqmp_ilp32_zu3eg description: | diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/optmgmtbase.yml b/spec/build/bsps/aarch64/xilinx-zynqmp/optmgmtbase.yml new file mode 100644 index 0000000000..8bb59e199b --- /dev/null +++ b/spec/build/bsps/aarch64/xilinx-zynqmp/optmgmtbase.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint64: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2022 On-Line Applications Research (OAR) +# The super_if_axi_uart16550_0 management UART exists in the FPGA fabric and may +# exist at different addresses such as 0x80090000. +default: 0x800a0000 +default-by-variant: [] +description: | + Base address of ZynqMP management UART +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_XILINX_ZYNQMP_MGMT_UART_BASE +type: build diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/optramori.yml b/spec/build/bsps/aarch64/xilinx-zynqmp/optramori.yml index c17febe288..427f14c7c8 100644 --- a/spec/build/bsps/aarch64/xilinx-zynqmp/optramori.yml +++ b/spec/build/bsps/aarch64/xilinx-zynqmp/optramori.yml @@ -11,6 +11,7 @@ default: 0x40018000 default-by-variant: - value: 0x10000000 variants: + - aarch64/xilinx_zynqmp_lp64_cfc400x - aarch64/xilinx_zynqmp_lp64_zu3eg - aarch64/xilinx_zynqmp_ilp32_zu3eg description: | diff --git a/spec/build/cpukit/optsmp.yml b/spec/build/cpukit/optsmp.yml index b218364194..db404efe21 100644 --- a/spec/build/cpukit/optsmp.yml +++ b/spec/build/cpukit/optsmp.yml @@ -13,6 +13,7 @@ description: | enabled-by: - aarch64/xilinx_zynqmp_ilp32_qemu - aarch64/xilinx_zynqmp_ilp32_zu3eg +- aarch64/xilinx_zynqmp_lp64_cfc400x - aarch64/xilinx_zynqmp_lp64_qemu - aarch64/xilinx_zynqmp_lp64_zu3eg - arm/altcycv_devkit -- 2.30.2 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel