Hi Sebastian, > On Mon, 2022-11-21 at 10:53 +0100, Sebastian Huber wrote: > > On 21/11/2022 10:50, padmarao.beg...@microchip.com wrote: > > The interrupt number(vector) mention in the device tree node is > > working > > when the driver is used the RISCV_INTERRUPT_VECTOR_EXTERNAL() and > > later > > called the RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX() in the RTEMS > > but > > the interrupt number is decreased by 2 when registering the > > interrupt > > from the RTEMS-LIBBSD driver(ex: Cadence GEM). The RTEMS-LIBBSD > > doesn't > > call the RISCV_INTERRUPT_VECTOR_EXTERNAL() but called the > > RISCV_INTERRU > > PT_VECTOR_EXTERNAL_TO_INDEX() for interrupt enable. > > > > In "bsps/riscv/riscv/include/bsp/irq.h" > > > > #define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2) > > > > #define RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2) > > > > #define RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2) > > > > Can we create a config file for non-external interrupt vector index > > instead of '2'? > > > > like '2' for RISC-V GENERIC and '0' for PolarFire SoC. > > To which number would you map the software and timer interrupts? >
The Software and Timer interrupts(numbers 0 & 1) are mapped by the Machine cause register (mcause) and enabled by the CLINT but not by the PLIC. > Can't this off by two problem be fixed by bsp_fdt_map_intr()? will check this option. Regards Padmarao > -- > embedded brains GmbH > Herr Sebastian HUBER > Dornierstr. 4 > 82178 Puchheim > Germany > email: sebastian.hu...@embedded-brains.de > phone: +49-89-18 94 741 - 16 > fax: +49-89-18 94 741 - 08 > > Registergericht: Amtsgericht München > Registernummer: HRB 157899 > Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas > Dörfler > Unsere Datenschutzerklärung finden Sie hier: > https://embedded-brains.de/datenschutzerklaerung/ _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel