This looks exciting. As for Versal support from Xilinx's Docs "RPU
The real-time processing unit (RPU) Arm Cortex-R5F processor has faster clocking frequencies than the Zynq UltraScale+ MPSoC. The Versal Arm Cortex-R5F processor supports Vector Floating-Point v3 (VFPv3) whereas the Zynq UltraScale+ MPSoC Arm Cortex-R5F processor supports VFPv2." https://docs.xilinx.com/r/en-US/ug1273-versal-acap-design/RPU VFPv3 is backwards compatible with VFPv2 (https://developer.arm.com/documentation/ddi0344/d/programmer-s-model/vfpv3-architecture?lang=en). So hopefully reuse for the Versal should relativity straight forward. Side note, even though Xilinx says the R5F in the ZynqMP has VFPv2, ARM says to compile with vfpv3_d16 like what is already in the BSP (https://developer.arm.com/documentation/dui0472/i/CIHGDBHC). Thanks, Aaron ------- Original Message ------- On Thursday, June 15th, 2023 at 9:17 AM, Chris Johns <chr...@rtems.org> wrote: > > > On 14/6/2023 6:08 pm, Philip Kirkpatrick wrote: > > > This patch adds support for running RTEMS on the RPU (cortex R5) cores of > > the > > ZynqMP. > > > Thanks for submitting this BSP. It is exciting to see this work and support > being added. > > How different are the ZynqMP RPU cores and the ones on the Versal? > > I have not looked in detail but I know they are both R5 devices and I think we > should be able to reuse this support. Is placing the RPU pieces under the > ZynqMP > sources what we want or should we consider how we would reuse the RPU BSP on > other Xilinx devices? > > I am leading with this question without reviewing the sources in detail so I > apologise for this. I am happy to look at Versal support so I am not asking > that > to be done. > > Chris > _______________________________________________ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel