On 7/11/2023 4:58 PM, Karel Gardas wrote:
On 7/11/23 23:26, Kinsey Moore wrote:
I'm not sure that anything I've done for testing would have verified
that the SDRAM is operating properly. I'll have to pull it back out
and give it a shot.
If you write just few char or integer into the beginning of both
regions you will see which one is working and which not. When "not"
happen RTEMS will crash nicely.
btw: be aware of partial write like just a char or two. The MCU have
ECC support permanently on and such partial writes may be and are
delayed in expectation that more will write will happen soon and no
need to update ECC bits. In that case you would also need to write
somewhere else to enforce previous write to be committed...STMicro has
a nice application note about it: AN5342.
I'm really curious what would be your result.
I took a look at an example application for this board in STM32CubeIDE
and it's expecting SDRAM to be at 0xD0000000U which is definitely bank
2. I'll get that updated and verified. Thanks for the review!
Kinsey
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