---
bsps/arm/tms570/start/bspstarthooks-hwinit.c | 2 ++
bsps/arm/tms570/start/tms570_tcram_tests.c | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/bsps/arm/tms570/start/bspstarthooks-hwinit.c
b/bsps/arm/tms570/start/bspstarthooks-hwinit.c
index c42200d80a..a0d80da2a9 100644
--- a/bsps/arm/tms570/start/bspstarthooks-hwinit.c
+++ b/bsps/arm/tms570/start/bspstarthooks-hwinit.c
@@ -229,6 +229,7 @@ static RTEMS_USED void tms570_start_hook_0( void )
if ( !tms570_running_from_tcram() ) {
+#if TMS570_VARIANT == 3137
/* Test the CPU ECC mechanism for RAM accesses.
* The checkBxRAMECC functions cause deliberate single-bit and double-bit
errors in TCRAM accesses
* by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location
with a 2-bit error
@@ -237,6 +238,7 @@ static RTEMS_USED void tms570_start_hook_0( void )
* following the one that caused the abort.
*/
tms570_check_tcram_ecc();
+#endif
/* Wait for PBIST for CPU RAM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
diff --git a/bsps/arm/tms570/start/tms570_tcram_tests.c
b/bsps/arm/tms570/start/tms570_tcram_tests.c
index 2103bc61ff..edfd441874 100644
--- a/bsps/arm/tms570/start/tms570_tcram_tests.c
+++ b/bsps/arm/tms570/start/tms570_tcram_tests.c
@@ -57,6 +57,8 @@
#include <bsp/tms570_selftest.h>
#include <bsp/tms570_hwinit.h>
+#if TMS570_VARIANT == 3137
+
#define tcramA1bitError (*(volatile uint32_t *)(0x08400000U))
#define tcramA2bitError (*(volatile uint32_t *)(0x08400010U))
@@ -181,3 +183,5 @@ void tms570_check_tcram_ecc( void )
tcramA2bit = tcramA2_bk;
tcramB2bit = tcramB2_bk;
}
+
+#endif /* TMS570_VARIANT */
--
2.35.3
_______________________________________________
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
