A few comments inline below. For the most part, this looks good. On Sat, Jan 6, 2024 at 9:15 AM <berndmoessne...@gmail.com> wrote:
> From: Bernd Moessner <berndmoessne...@gmail.com> > > This patch adds support for the Xilinx ZYNQ 7000 series. Please note that > this patch also affects ZYNQ Ultrascale+ as I`ve moved some functions from > zynqmp/xil_shims.c to xilinx/freertos.c and xilinx/xscugic.c to share them > between both families. > --- > defs/bsps/aarch64/xilinx_zynqmp_base.json | 2 + > defs/bsps/arm/xilinx_zynq_base.json | 28 ++++++ > defs/bsps/arm/xilinx_zynq_picozed.json | 13 +++ > .../ports/xilinx/include/netif/xadapter.h | 4 + > .../contrib/ports/xilinx/netif/xemacpsif.c | 18 ++++ > .../ports/xilinx/netif/xemacpsif_dma.c | 14 +++ > .../bsp/standalone/src/arm/cortexa9/xil_mmu.h | 92 +++++++++++++++++++ > rtemslwip/xilinx/freertos.c | 64 +++++++++++++ > rtemslwip/xilinx/xpseudo_asm.h | 5 + > rtemslwip/xilinx/xscugic_hw.c | 40 ++++++++ > rtemslwip/zynq/common_lwipopts.h | 3 + > rtemslwip/zynq/xil_shims.c | 42 +++++++++ > rtemslwip/zynq/xlwipconfig.h | 38 ++++++++ > rtemslwip/zynq_picozed/lwipbspopts.h | 1 + > rtemslwip/zynq_picozed/netstart.c | 66 +++++++++++++ > rtemslwip/zynq_picozed/xemacps_g.c | 35 +++++++ > rtemslwip/zynq_picozed/xparameters_ps.h | 72 +++++++++++++++ > rtemslwip/zynq_picozed/xtopology_g.c | 40 ++++++++ > rtemslwip/zynqmp/xil_shims.c | 45 --------- > 19 files changed, 577 insertions(+), 45 deletions(-) > create mode 100644 defs/bsps/arm/xilinx_zynq_base.json > create mode 100644 defs/bsps/arm/xilinx_zynq_picozed.json > create mode 100644 > embeddedsw/lib/bsp/standalone/src/arm/cortexa9/xil_mmu.h > create mode 100644 rtemslwip/xilinx/freertos.c > create mode 100644 rtemslwip/xilinx/xscugic_hw.c > create mode 100644 rtemslwip/zynq/common_lwipopts.h > create mode 100644 rtemslwip/zynq/xil_shims.c > create mode 100644 rtemslwip/zynq/xlwipconfig.h > create mode 100644 rtemslwip/zynq_picozed/lwipbspopts.h > create mode 100644 rtemslwip/zynq_picozed/netstart.c > create mode 100644 rtemslwip/zynq_picozed/xemacps_g.c > create mode 100644 rtemslwip/zynq_picozed/xparameters_ps.h > create mode 100644 rtemslwip/zynq_picozed/xtopology_g.c > > diff --git a/defs/bsps/aarch64/xilinx_zynqmp_base.json > b/defs/bsps/aarch64/xilinx_zynqmp_base.json > index 600415d..f8f4c14 100644 > --- a/defs/bsps/aarch64/xilinx_zynqmp_base.json > +++ b/defs/bsps/aarch64/xilinx_zynqmp_base.json > @@ -9,6 +9,8 @@ > "embeddedsw/lib/bsp/standalone/src/arm/ARMv8/64bit" > ], > "source-files-to-import": [ > + "rtemslwip/xilinx/freertos.c", > + "rtemslwip/xilinx/xscugic_hw.c", > "rtemslwip/zynqmp/xemacps_g.c", > "rtemslwip/zynqmp/xil_shims.c", > "rtemslwip/zynqmp/xtopology_g.c", > diff --git a/defs/bsps/arm/xilinx_zynq_base.json > b/defs/bsps/arm/xilinx_zynq_base.json > new file mode 100644 > index 0000000..aad0640 > --- /dev/null > +++ b/defs/bsps/arm/xilinx_zynq_base.json > @@ -0,0 +1,28 @@ > +{ > + "header-paths-to-import": [ > + > "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/include", > + "embeddedsw/lib/bsp/standalone/src/common", > + "embeddedsw/XilinxProcessorIPLib/drivers/scugic/src", > + "embeddedsw/XilinxProcessorIPLib/drivers/emacps/src", > + "rtemslwip/xilinx", > + "rtemslwip/zynq", > + "embeddedsw/lib/bsp/standalone/src/arm/cortexa9", > + "embeddedsw/lib/bsp/standalone/src/arm/common" > + ], > + "source-files-to-import": [ > + "rtemslwip/zynq/xil_shims.c", > + "rtemslwip/xilinx/freertos.c", > + "rtemslwip/xilinx/xscugic_hw.c", > + > > "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xadapter.c", > + > > "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xpqueue.c", > + > > "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif.c", > + > > "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_dma.c", > + > > "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_hw.c", > + > > "embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c", > + > "embeddedsw/XilinxProcessorIPLib/drivers/emacps/src/xemacps_bdring.c", > + > "embeddedsw/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c", > + > "embeddedsw/XilinxProcessorIPLib/drivers/emacps/src/xemacps_control.c", > + > "embeddedsw/XilinxProcessorIPLib/drivers/emacps/src/xemacps_intr.c", > + "embeddedsw/lib/bsp/standalone/src/common/xil_assert.c" > + ] > +} > diff --git a/defs/bsps/arm/xilinx_zynq_picozed.json > b/defs/bsps/arm/xilinx_zynq_picozed.json > new file mode 100644 > index 0000000..feb4188 > --- /dev/null > +++ b/defs/bsps/arm/xilinx_zynq_picozed.json > @@ -0,0 +1,13 @@ > +{ > + "includes": [ > + "xilinx_zynq_base" > + ], > + "header-paths-to-import": [ > + "rtemslwip/zynq_picozed" > + ], > + "source-files-to-import": [ > + "rtemslwip/zynq_picozed/xemacps_g.c", > + "rtemslwip/zynq_picozed/xtopology_g.c", > + "rtemslwip/zynq_picozed/netstart.c" > + ] > +} > diff --git > a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/include/netif/xadapter.h > b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/include/netif/xadapter.h > index 4d32b7f..aa491b7 100644 > --- > a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/include/netif/xadapter.h > +++ > b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/include/netif/xadapter.h > @@ -53,7 +53,11 @@ struct xemac_s { > #if !NO_SYS > sys_sem_t sem_rx_data_available; > #if defined(__arm__) && !defined(ARMR5) > +#ifndef __rtems__ > TimerHandle_t xTimer; > +#else /* __rtems__ */ > + rtems_id xTimer; > +#endif > #endif > #endif > }; > diff --git > a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif.c > b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif.c > index 5328e86..3e36771 100644 > --- > a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif.c > +++ > b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif.c > @@ -329,11 +329,19 @@ s32_t xemacpsif_input(struct netif *netif) > > #if !NO_SYS > #if defined(__arm__) && !defined(ARMR5) > +#ifndef __rtems__ > void vTimerCallback( TimerHandle_t pxTimer ) > { > /* Do something if the pxTimer parameter is NULL */ > configASSERT(pxTimer); > > +#else /* __rtems__ */ > +static rtems_timer_service_routine vTimerCallback( > + rtems_id timer, > + void *arg > +) > +{ > +#endif > I'm surprised you're not getting warnings for unused arguments for timer and arg. > lExpireCounter++; > /* If the timer has expired 100 times then reset RX */ > if(lExpireCounter >= RESETRXTIMEOUT) { > @@ -434,6 +442,7 @@ static err_t low_level_init(struct netif *netif) > > XEMACPS_DMACR_OFFSET, dmacrreg); > #if !NO_SYS > #if defined(__arm__) && !defined(ARMR5) > +#ifndef __rtems__ > /* Freertos tick is 10ms by default; set period to the same */ > xemac->xTimer = xTimerCreate("Timer", 10, pdTRUE, ( void * ) 1, > vTimerCallback); > if (xemac->xTimer == NULL) { > @@ -443,6 +452,15 @@ static err_t low_level_init(struct netif *netif) > xil_printf("In %s:Timer start failed....\r\n", > __func__); > } > } > +#else /* __rtems__ */ > + rtems_status_code ret = rtems_timer_create( rtems_build_name( 'L', > 'W', 'M', 'R' ), &xemac->xTimer); > + if(RTEMS_SUCCESSFUL == ret){ > + ret = rtems_timer_fire_after(xemac->xTimer, > rtems_clock_get_ticks_per_second()/100, vTimerCallback, NULL); > + } > + if(RTEMS_SUCCESSFUL != ret){ > + xil_printf("In %s:Timer setup failed....\r\n", __func__); > + } > Indentation doesn't match surrounding code. > +#endif > #endif > #endif > setup_isr(xemac); > diff --git > a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_dma.c > b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_dma.c > index 1d2439a..c222835 100644 > --- > a/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_dma.c > +++ > b/embeddedsw/ThirdParty/sw_services/lwip211/src/contrib/ports/xilinx/netif/xemacpsif_dma.c > @@ -114,7 +114,15 @@ volatile u32_t notifyinfo[4*XLWIP_CONFIG_N_TX_DESC]; > #if defined __aarch64__ > u8_t bd_space[0x200000] __attribute__ ((aligned (0x200000))); > #else > +#ifndef __rtems__ > u8_t bd_space[0x100000] __attribute__ ((aligned (0x100000))); > +#else /* __rtems__ */ > +#if defined(__arm__) && !defined(ARMR5) > +u8_t bd_space[0x100000] __attribute__ ((section(".bsp_nocache"), aligned > (0x100000))); > +#else > +u8_t bd_space[0x100000] __attribute__ ((aligned (0x100000))); > +#endif > +#endif > Is there a reason you chose to change this interface instead of defining Xil_SetTlbAttributes to use arm_cp15_start_set_translation_table_entries(bsp_translation_table_base, ...)? The struct passed as the second parameter only needs to exist for the duration of the function call. > #endif > static volatile u32_t bd_space_index = 0; > static volatile u32_t bd_space_attr_set = 0; > @@ -676,7 +684,13 @@ XStatus init_dma(struct xemac_s *xemac) > #if defined __aarch64__ > Xil_SetTlbAttributes((u64)bd_space, NORM_NONCACHE | > INNER_SHAREABLE); > #else > +#ifndef __rtems__ > Xil_SetTlbAttributes((s32_t)bd_space, DEVICE_MEMORY); // addr, attr > +#else /* __rtems__ */ > +#if !defined(__arm__) > + Xil_SetTlbAttributes((s32_t)bd_space, DEVICE_MEMORY); // addr, attr > +#endif > +#endif > #endif > #endif > bd_space_attr_set = 1; > With the current configuration not using any of the identifiers defined here, this file import (cortexa9/xil_mmu.h) would be better served by a blank stub file. You'll need it if you define Xil_SetTlbAttributes, instead. > diff --git a/embeddedsw/lib/bsp/standalone/src/arm/cortexa9/xil_mmu.h > b/embeddedsw/lib/bsp/standalone/src/arm/cortexa9/xil_mmu.h > new file mode 100644 > index 0000000..d21e13a > --- /dev/null > +++ b/embeddedsw/lib/bsp/standalone/src/arm/cortexa9/xil_mmu.h > @@ -0,0 +1,92 @@ > > +/****************************************************************************** > +* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved. > +* SPDX-License-Identifier: MIT > > +******************************************************************************/ > + > > +/*****************************************************************************/ > +/** > +* @file xil_mmu.h > +* > +* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions > +* > +* MMU functions equip users to enable MMU, disable MMU and modify default > +* memory attributes of MMU table as per the need. > +* > +* @{ > +* > +* <pre> > +* MODIFICATION HISTORY: > +* > +* Ver Who Date Changes > +* ----- ---- -------- --------------------------------------------------- > +* 1.00a sdm 01/12/12 Initial version > +* 4.2 pkp 07/21/14 Included xil_types.h file which contains > definition for > +* u32 which resolves issue of > CR#805869 > +* 5.4 pkp 23/11/15 Added attribute definitions for > Xil_SetTlbAttributes API > +* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. > +* </pre> > +* > +* > > +******************************************************************************/ > + > +/** > +*@cond nocomments > +*/ > + > +#ifndef XIL_MMU_H > +#define XIL_MMU_H > + > +#ifdef __cplusplus > +extern "C" { > +#endif /* __cplusplus */ > + > +/***************************** Include Files > *********************************/ > + > +#include "xil_types.h" > + > +/***************** Macros (Inline Functions) Definitions > *********************/ > + > +/**************************** Type Definitions > *******************************/ > + > +/************************** Constant Definitions > *****************************/ > + > +/* Memory type */ > +#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */ > +#define STRONG_ORDERED 0xC02 /* Strongly ordered */ > +#define DEVICE_MEMORY 0xC06 /* Device memory */ > +#define RESERVED 0x0 /* reserved memory */ > + > +/* Normal write-through cacheable shareable */ > +#define NORM_WT_CACHE 0x16DEA > + > +/* Normal write back cacheable shareable */ > +#define NORM_WB_CACHE 0x15DE6 > + > +/* shareability attribute */ > +#define SHAREABLE (0x1 << 16) > +#define NON_SHAREABLE (~(0x1 << 16)) > + > +/* Execution type */ > +#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0)) > + > +/** > +*@endcond > +*/ > + > +/************************** Variable Definitions > *****************************/ > + > +/************************** Function Prototypes > ******************************/ > + > +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib); > +void Xil_EnableMMU(void); > +void Xil_DisableMMU(void); > +void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags); > + > +#ifdef __cplusplus > +} > +#endif /* __cplusplus */ > + > +#endif /* XIL_MMU_H */ > +/** > +* @} End of "addtogroup a9_mmu_apis". > +*/ > diff --git a/rtemslwip/xilinx/freertos.c b/rtemslwip/xilinx/freertos.c > new file mode 100644 > index 0000000..90d1f83 > --- /dev/null > +++ b/rtemslwip/xilinx/freertos.c > @@ -0,0 +1,64 @@ > +/* > + * Copyright (C) 2024 On-Line Applications Research Corporation (OAR) > + * Written by Kinsey Moore <kinsey.mo...@oarcorp.com> > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions > + * are met: > + * 1. Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * 2. Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in the > + * documentation and/or other materials provided with the distribution. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > "AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, > THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR > PURPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS > BE > + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR > + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF > + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR > BUSINESS > + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN > + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) > + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF > THE > + * POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#include <rtems/rtems/intr.h> > +#include <rtems/score/threadimpl.h> > +#include <stdio.h> > +#include <string.h> > +#include "xil_types.h" > +#include "FreeRTOS.h" > + > + > +/* > + * XInterruptHandler function pointer signature just happens to exactly > match > + * rtems_interrupt_handler > + */ > +BaseType_t xPortInstallInterruptHandler( > + uint8_t ucInterruptID, > + XInterruptHandler pxHandler, > + void *pvCallBackRef > +) > +{ > + char name[10]; > + > + /* Is this running in the context of any interrupt server tasks? */ > + _Thread_Get_name( _Thread_Get_executing(), name, sizeof( name ) ); > + if (strcmp(name, "IRQS") == 0) { > + /* Can't run this from within an IRQ Server thread context */ > + return RTEMS_ILLEGAL_ON_SELF; > + } > + > + rtems_status_code sc = rtems_interrupt_server_handler_install( > + RTEMS_INTERRUPT_SERVER_DEFAULT, > + ucInterruptID, > + "CGEM Handler", > + RTEMS_INTERRUPT_UNIQUE, > + pxHandler, > + pvCallBackRef > + ); > + > + return sc; > +} > diff --git a/rtemslwip/xilinx/xpseudo_asm.h > b/rtemslwip/xilinx/xpseudo_asm.h > index cb51433..0168ce3 100644 > --- a/rtemslwip/xilinx/xpseudo_asm.h > +++ b/rtemslwip/xilinx/xpseudo_asm.h > @@ -28,6 +28,11 @@ > #define XPSEUDO_ASM_H > > #include <rtems/score/cpu.h> > +#if defined(__arm__) && !defined(ARMR5) > +#define dsb() _ARM_Data_synchronization_barrier() > +#define isb() _ARM_Instruction_synchronization_barrier() > +#else > #define dsb() _AARCH64_Data_synchronization_barrier() > +#endif > > #endif > diff --git a/rtemslwip/xilinx/xscugic_hw.c b/rtemslwip/xilinx/xscugic_hw.c > new file mode 100644 > index 0000000..9ba14a4 > --- /dev/null > +++ b/rtemslwip/xilinx/xscugic_hw.c > @@ -0,0 +1,40 @@ > +/* > + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) > + * Written by Kinsey Moore <kinsey.mo...@oarcorp.com> > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions > + * are met: > + * 1. Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * 2. Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in the > + * documentation and/or other materials provided with the distribution. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > "AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, > THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR > PURPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS > BE > + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR > + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF > + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR > BUSINESS > + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN > + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) > + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF > THE > + * POSSIBILITY OF SUCH DAMAGE. > + */ > + > + #include <rtems/rtems/intr.h> > +#include "xil_types.h" > + > +/* Enable the interrupt */ > +void XScuGic_EnableIntr ( u32 DistBaseAddress, u32 Int_Id ) > +{ > + rtems_interrupt_vector_enable( Int_Id ); > +} > + > +/* Disable the interrupt */ > +void XScuGic_DisableIntr ( u32 DistBaseAddress, u32 Int_Id ) > +{ > + rtems_interrupt_vector_disable( Int_Id ); > +} > diff --git a/rtemslwip/zynq/common_lwipopts.h > b/rtemslwip/zynq/common_lwipopts.h > new file mode 100644 > index 0000000..8b7d870 > --- /dev/null > +++ b/rtemslwip/zynq/common_lwipopts.h > @@ -0,0 +1,3 @@ > +#include <xparameters_ps.h> > +#include <xlwipopts.h> > +#define MEM_ALIGNMENT 64 > diff --git a/rtemslwip/zynq/xil_shims.c b/rtemslwip/zynq/xil_shims.c > new file mode 100644 > index 0000000..50afcf8 > --- /dev/null > +++ b/rtemslwip/zynq/xil_shims.c > @@ -0,0 +1,42 @@ > +/* > + * SPDX-License-Identifier: BSD-2-Clause > + * > + * Copyright (C) 2024 Bernd Moessner > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions > + * are met: > + * 1. Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * 2. Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in the > + * documentation and/or other materials provided with the distribution. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > "AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, > THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR > PURPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS > BE > + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR > + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF > + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR > BUSINESS > + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN > + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) > + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF > THE > + * POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#include "xil_mmu.h" > +#include <rtems/rtems/cache.h> > +#include <stdio.h> > +#include <string.h> > + > + > +void Xil_DCacheInvalidateRange( INTPTR adr, INTPTR len ) > +{ > + rtems_cache_flush_multiple_data_lines( (const void *) adr, len ); > +} > + > +void Xil_DCacheFlushRange( INTPTR adr, INTPTR len ) > +{ > + Xil_DCacheInvalidateRange(adr, len ); > +} > diff --git a/rtemslwip/zynq/xlwipconfig.h b/rtemslwip/zynq/xlwipconfig.h > new file mode 100644 > index 0000000..8144153 > --- /dev/null > +++ b/rtemslwip/zynq/xlwipconfig.h > @@ -0,0 +1,38 @@ > +/* > + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) > + * Written by Kinsey Moore <kinsey.mo...@oarcorp.com> > You should replace the copyright information here. > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions > + * are met: > + * 1. Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * 2. Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in the > + * documentation and/or other materials provided with the distribution. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > "AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, > THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR > PURPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS > BE > + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR > + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF > + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR > BUSINESS > + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN > + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) > + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF > THE > + * POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#ifndef __XLWIPCONFIG_H_ > +#define __XLWIPCONFIG_H_ > + > +#define XLWIP_CONFIG_INCLUDE_GEM 1 > +#define XLWIP_CONFIG_EMAC_NUMBER 0 > +#define XLWIP_CONFIG_N_TX_DESC 64 > +#define XLWIP_CONFIG_N_RX_DESC 64 > + > +#define XLWIP_CONFIG_N_TX_COALESCE 1 > +#define XLWIP_CONFIG_N_RX_COALESCE 1 > + > +#endif > diff --git a/rtemslwip/zynq_picozed/lwipbspopts.h > b/rtemslwip/zynq_picozed/lwipbspopts.h > new file mode 100644 > index 0000000..143e302 > --- /dev/null > +++ b/rtemslwip/zynq_picozed/lwipbspopts.h > @@ -0,0 +1 @@ > +#include <common_lwipopts.h> > diff --git a/rtemslwip/zynq_picozed/netstart.c > b/rtemslwip/zynq_picozed/netstart.c > new file mode 100644 > index 0000000..2f11979 > --- /dev/null > +++ b/rtemslwip/zynq_picozed/netstart.c > @@ -0,0 +1,66 @@ > +/* > + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) > + * Written by Kinsey Moore <kinsey.mo...@oarcorp.com> > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions > + * are met: > + * 1. Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * 2. Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in the > + * documentation and/or other materials provided with the distribution. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > "AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, > THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR > PURPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS > BE > + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR > + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF > + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR > BUSINESS > + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN > + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) > + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF > THE > + * POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#include <netstart.h> > +#include "netif/xadapter.h" > +#include "xparameters.h" > +#include <lwip/tcpip.h> > + > +int start_networking( > + struct netif *net_interface, > + ip_addr_t *ipaddr, > + ip_addr_t *netmask, > + ip_addr_t *gateway, > + unsigned char *mac_ethernet_address > +) > +{ > + start_networking_shared(); > + > + if ( !xemac_add( > + net_interface, > + ipaddr, > + netmask, > + gateway, > + mac_ethernet_address, > + XPAR_PS7_ETHERNET_0_BASEADDR > + ) ) { > + return 1; > + } > + > + netif_set_default( net_interface ); > + > + netif_set_up( net_interface ); > + > + sys_thread_new( > + "xemacif_input_thread", > + ( void ( * )( void * ) )xemacif_input_thread, > + net_interface, > + 1024, > + DEFAULT_THREAD_PRIO > + ); > No changes currently required here, but fair warning that I have a patch coming soon that will affect the ZynqMP netstart code. I've received confirmation from Xilinx/AMD that the emacps driver was never meant to be SMP-capable (and it really isn't). This thread creation will be locked to core 0 with the IRQ server servicing thread. I'll update this code when I update the ZynqMP code. > + > + return 0; > +} > diff --git a/rtemslwip/zynq_picozed/xemacps_g.c > b/rtemslwip/zynq_picozed/xemacps_g.c > new file mode 100644 > index 0000000..596bc49 > --- /dev/null > +++ b/rtemslwip/zynq_picozed/xemacps_g.c > @@ -0,0 +1,35 @@ > +/******************************************************************* > +* > +* CAUTION: This file is automatically generated by HSI. > +* Version: 2021.2 > +* DO NOT EDIT. > +* > +* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved. > +* SPDX-License-Identifier: MIT > +* > +* Description: Driver configuration > +* > +*******************************************************************/ > + > +#include "xparameters.h" > +#include "xparameters_ps.h" > +#include "xemacps.h" > + > +/* > +* The configuration table for devices > +*/ > + > This should be made more generic and shared among Zynq hardware if possible by adding the other ethernet interface. > +XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] = > +{ > + { > + XPAR_PS7_ETHERNET_0_DEVICE_ID, > + XPAR_PS7_ETHERNET_0_BASEADDR, > + XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT, > + XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0, > + XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1, > + XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0, > + XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1, > + XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0, > + XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 > + } > +}; > diff --git a/rtemslwip/zynq_picozed/xparameters_ps.h > b/rtemslwip/zynq_picozed/xparameters_ps.h > new file mode 100644 > index 0000000..d88a3fe > --- /dev/null > +++ b/rtemslwip/zynq_picozed/xparameters_ps.h > @@ -0,0 +1,72 @@ > +/* > + * SPDX-License-Identifier: BSD-2-Clause > + * > + * Copyright (C) 2024 Bernd Moessner > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions > + * are met: > + * 1. Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * 2. Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in the > + * documentation and/or other materials provided with the distribution. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > "AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, > THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR > PURPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS > BE > + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR > + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF > + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR > BUSINESS > + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN > + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) > + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF > THE > + * POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#ifndef _XPARAMETERS_PS_H_ > +#define _XPARAMETERS_PS_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U > +#define XPS_SYS_CTRL_BASEADDR 0xF8000000U > + > +#define XPAR_XEMACPS_NUM_INSTANCES 1 > + > +#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0 > +#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000 > +#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF > +#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000 > +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8 > +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1 > +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8 > +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5 > +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8 > +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50 > +#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0 > + > +#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0 > +#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0 > + > +#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID > +#define XPAR_XEMACPS_0_BASEADDR 0xE000B000 > +#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF > +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000 > +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8 > +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 > +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8 > +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5 > +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8 > +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50 > +#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0 > + > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif > diff --git a/rtemslwip/zynq_picozed/xtopology_g.c > b/rtemslwip/zynq_picozed/xtopology_g.c > new file mode 100644 > index 0000000..bf0ee25 > --- /dev/null > +++ b/rtemslwip/zynq_picozed/xtopology_g.c > @@ -0,0 +1,40 @@ > +/* > + * Copyright (C) 2024 Bernd Moessner > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions > + * are met: > + * 1. Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * 2. Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in the > + * documentation and/or other materials provided with the distribution. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > "AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, > THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR > PURPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS > BE > + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR > + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF > + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR > BUSINESS > + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN > + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) > + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF > THE > + * POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#include "netif/xtopology.h" > +#include "xparameters.h" > + > This should be made more generic and shared among Zynq hardware if possible by adding the other ethernet interface > +struct xtopology_t xtopology[] = { > + { > + 0xE000B000, > + xemac_type_emacps, > + 0x0, > + 0x0, > + 0xF8F00100, > + 0x36, > + }, > +}; > + > +int xtopology_n_emacs = 1; > diff --git a/rtemslwip/zynqmp/xil_shims.c b/rtemslwip/zynqmp/xil_shims.c > index 1b1b3cf..1b566b6 100644 > --- a/rtemslwip/zynqmp/xil_shims.c > +++ b/rtemslwip/zynqmp/xil_shims.c > @@ -57,51 +57,6 @@ void Xil_SetTlbAttributes( UINTPTR Addr, u64 attrib ) > } > } > > -#include "FreeRTOS.h" > - > -/* > - * XInterruptHandler function pointer signature just happens to exactly > match > - * rtems_interrupt_handler > - */ > -BaseType_t xPortInstallInterruptHandler( > - uint8_t ucInterruptID, > - XInterruptHandler pxHandler, > - void *pvCallBackRef > -) > -{ > - char name[10]; > - > - /* Is this running in the context of any interrupt server tasks? */ > - _Thread_Get_name( _Thread_Get_executing(), name, sizeof( name ) ); > - if (strcmp(name, "IRQS") == 0) { > - /* Can't run this from within an IRQ Server thread context */ > - return RTEMS_ILLEGAL_ON_SELF; > - } > - > - rtems_status_code sc = rtems_interrupt_server_handler_install( > - RTEMS_INTERRUPT_SERVER_DEFAULT, > - ucInterruptID, > - "CGEM Handler", > - RTEMS_INTERRUPT_UNIQUE, > - pxHandler, > - pvCallBackRef > - ); > - > - return sc; > -} > - > -/* Enable the interrupt */ > -void XScuGic_EnableIntr ( u32 DistBaseAddress, u32 Int_Id ) > -{ > - rtems_interrupt_vector_enable( Int_Id ); > -} > - > -/* Disable the interrupt */ > -void XScuGic_DisableIntr ( u32 DistBaseAddress, u32 Int_Id ) > -{ > - rtems_interrupt_vector_disable( Int_Id ); > -} > - > /* > * The Xilinx code was written such that it assumed there was no > invalidate-only > * functionality on A53 cores. This function must flush and invalidate > because > -- > 2.34.1 > > _______________________________________________ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel >
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