Hi Sebastian, Chris,

> I am not sure about this patch. It changes the initialization. The code
> you remove was added by:
> commit 691d0edd34f25a883c5dd0a56051d087b88e4fa4
> Author: Chris Johns <chr...@rtems.org>
> Date:   Tue Aug 17 17:57:41 2021 +1000
>      arm/xilinx: Fix zynq-uart interrupt receive
>      - Trigger on a single character entering the RX FIFO
>      - Disable the RX timeout
>      - Send up to a FIFO full of data

As I wrote in the commit message, I think that a UART driver should not send 
any characters without being explicitely told so. The protocol that I'm using 
gets confused as it does not expect these bytes.

I've indeed seen the commit you reference, and the call to 
`zynq_uart_reset_tx_flush()` which sends these bytes seems to me unrelated to 
the bug the commit fixes, which is about the receive interrupt. As such, I 
believe that my patch should be merged (at least from a functionality point of 
view, I don't have any feelings about the implementation. For ex, passing a 
flag "text"/"raw" or having a global variable "char *initialization_tx_bytes" 
could also work, although that might not be compatible with the TERMIOS/POSIX 
way of doing things).

That being said, I'm only arguing my particular case, and you as maintainers 
have the final word.

I'm available if you need anything else from me.

Best regards,
Adrien Chardon

________________________________
From: Sebastian Huber <sebastian.hu...@embedded-brains.de>
Sent: 01 February 2024 08:03
To: devel@rtems.org <devel@rtems.org>
Cc: Chris Johns <chr...@rtems.org>; Adrien Chardon <adr...@reflexaerospace.com>
Subject: Re: [Patch] bsp/tms570/sci: fix bug in tms570_sci_read_received_chars()

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Hello Adrien,

On 31.01.24 18:35, Adrien Chardon wrote:
>
> While testing the counterpart of my protocol on a Zynq, I found a
> similar issue
> where the UART is assumed to be used for printable text only. The second
> patch
> fixes it.

I am not sure about this patch. It changes the initialization. The code
you remove was added by:

commit 691d0edd34f25a883c5dd0a56051d087b88e4fa4
Author: Chris Johns <chr...@rtems.org>
Date:   Tue Aug 17 17:57:41 2021 +1000

     arm/xilinx: Fix zynq-uart interrupt receive

     - Trigger on a single character entering the RX FIFO

     - Disable the RX timeout

     - Send up to a FIFO full of data

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