Hi Jensen, The kernel must be given a timer that the user mode is not also given access to. You say 'some registers can be accessed by both kernel and libsel4platsupport', this means that those register should not be given out by the kernel. You must either a. Find a different timer for the kernel b. Find a different timer for user level In terms of finding timers you can get creative if you need to. On an old ARMv5 port (this port was deprecated a couple of years ago and removed from the current code base) the instruction counter on the PMU was used to generate a periodic interrupt.
Adrian On 17/04/15 19:37, Jensen Zhang wrote: Hello everyone, We have ported seL4 to allwinnerA20, although the cache cannot still work well. All tests passed, except for CACHEFLUSH0001 and CACHEFLUSH0002. A git clone can be gotten from here [1]. And the 'zener' directory in this project has a similar structure to sel4test. But there is a problem about TIMER API. For allwinnerA20, there are several registers (Timer IRQ Enable/Status Register) used by all timers. Both kernel and libsel4platsupport will use timers, and they have to use different timers. But some registers can be accessed by both kernel and libsel4platsupport. That's very dangerous! Because libsel4platsupport can disable the timer of kernel by modifying the register. How to solve this problem? [1] git clone http://elastos.org/review/HD-Elastos -- Jensen Zhang Tongji University _______________________________________________ Devel mailing list [email protected]<mailto:[email protected]> https://sel4.systems/lists/listinfo/devel ________________________________ The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments.
_______________________________________________ Devel mailing list [email protected] https://sel4.systems/lists/listinfo/devel
