Hi Andrew, The fault status (0x7) is a direct representation of the ARM FSR (Fault Status Register). You can find the details in the ARMv7 manual.
>From memory, 0x7 is some kind of synchronous abort, which is equivalent to a >segmentation fault. >From the address (0x0) it looks like a NULL pointer dereference. Looking at your code, the cause is clear. Your 'ops' structure needs to be initialised before it is passed to the device initialisation function. In particular, it is required that you provide a function that can be used for mapping the serial port device frame into the virtual address space of your thread. You might like to use the initialisation procedure of sel4test as a case study: https://github.com/seL4/sel4test/blob/master/apps/sel4test-driver/src/main.c#L434 You might also be interested in the seL4 wrapper library for the OS independent libplatsupport driver library: https://github.com/seL4/libsel4platsupport/blob/master/include/sel4platsupport/platsupport.h - Alex ________________________________________ From: Devel [[email protected]] on behalf of Andrew Shruhan [[email protected]] Sent: Tuesday, 22 September 2015 06:18 To: [email protected] Cc: Satish Sundar Subject: [seL4] Caught cap fault in send phase at address 0x0 Hello, I am attempting to create a simple program opening up a serial port on the Sabrelight. Attached is the source code and below is the console output. On other sel4 blogs with this problem uboot may have been the issue. I have used the u-boot as discribed on the supported hardware->sabrelight page with the same outcome. Any help would be appreciated. Thanks, U-Boot 2009.08-dirty (Sep 17 2015 - 14:58:04) CPU: Freescale i.MX6 family TO1.2 at 792 MHz Temperature: 36 C, calibration data 0x56a4bc7d mx6q pll1: 792MHz mx6q pll2: 528MHz mx6q pll3: 480MHz mx6q pll8: 50MHz ipg clock : 66000000Hz ipg per clock : 66000000Hz uart clock : 80000000Hz cspi clock : 60000000Hz ahb clock : 132000000Hz axi clock : 264000000Hz emi_slow clock: 132000000Hz ddr clock : 528000000Hz usdhc1 clock : 198000000Hz usdhc2 clock : 198000000Hz usdhc3 clock : 198000000Hz usdhc4 clock : 198000000Hz nfc clock : 24000000Hz Board: MX6Q-SABRELITE:[ POR] Boot Device: I2C I2C: ready DRAM: 1 GB MMC: FSL_USDHC: 0,FSL_USDHC: 1 JEDEC ID: 0xbf:0x25:0x41 Reading SPI NOR flash 0xc0000 [0x2000 bytes] -> ram 0x276009b8 SUCCESS *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: got MAC address from IIM: 00:19:b8:01:fd:6d FEC0 [PRIME] Hit any key to stop autoboot: 0 mmc1 is current device -- Trying fat on SD 1, partition 1 reading sel4-image 344564 bytes read ## Starting application at 0x20000000 ... ELF-loader started on CPU: ARM Ltd. Cortex-A9 r2p10 paddr=[20000000..2004c01f] ELF-loading image 'kernel' paddr=[10000000..10031fff] vaddr=[e0000000..e0031fff] virt_entry=e0000000 ELF-loading image 'hello-1' paddr=[10032000..1003ffff] vaddr=[8000..15fff] virt_entry=803c Enabling MMU and paging Jumping to kernel-image entry point... Bootstrapping kernel Caught cap fault in send phase at address 0x0 while trying to handle: vm fault on data at address 0x0 with status 0x7 in thread 0xffdfd900 "rootserver" at address 0x804 -- -Andrew Andrew P. Shruhan Research and Development Engineer III DocBox, Inc. 320 Nevada St Newton MA, 02460 Work: 857-598-2819 ext. 117 www.docboxmed.com<http://www.docboxinc.com/> ________________________________ The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments. _______________________________________________ Devel mailing list [email protected] https://sel4.systems/lists/listinfo/devel
