note that the am335x port does not enable all of the hardware blocks by default. Some of the hardware blocks are enabled by the bootloader before sel4 runs, but not all of them.
See the attached patch, which includes code in enableTimers for powering on addtional timer hardware blocks (required for running the refos port on am335x). You may need to use similar code to enable your uart block if it is not enabled. Tim On Fri, Oct 2, 2015 at 12:42 PM, Jeff Hieb <[email protected]> wrote: > Alex, > > Thanks, that worked to fix the device frame error. Still working on the > driver. > > It seems like the device frame is not "bound" to the physical memory? > > Here is what is printed while the kernel is loading that relates to the > frame (I think). > > (pd_drv_group_bin, pt_drv_group_bin_2, 300000, 0) > (frame_drv_group_bin_42, pd_drv_group_bin, rights=3, vaddr=300000, > vm_attribs=2). > > I checked that 300000 is what camkes passed through to my component as > "mem", but I am so far unable to get the UART to respond using reads and > writes to mem + offset. > > Is there some additional code I need to add somewhere or should reads and > writes to (mem + offset) write to physical memory? > > Thanks, > > Jeff > > > > > > Jeffrey L. Hieb > Department of Engineering Fundamentals > University of Louisville > Louisville Kentucky 40292 > (502) 852 0465 > > On 9/27/2015 9:34 AM, Alexander Kroh wrote: > >> Hi Jeff, >> >> seL4 populates the bootinfo structure for the root process. >> >> MMIO frame production is a data driven process using the following data >> structure: >> >> https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_seL4_seL4_blob_master_src_plat_am335x_machine_hardware.c-23L43&d=AwIFAg&c=SgMrq23dbjbGX6e0ZsSHgEZX6A4IAf1SO3AJ2bNrHlk&r=vxDfYJYhOaaufTHzA3yxVVn--9Yf3Ig5TrUiTFGL8pc&m=xES3WJjaY0BbvKig8sNNQD6C8RdHjP2OrtyIzDDzCSQ&s=PE4Vs_EGQB_z2P9KgLYL6Af6ZPkogMq6FGz3RmEPyeY&e= >> >> FYI, the physical address of device frames are defined here: >> >> https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_seL4_seL4_blob_master_include_plat_am335x_plat_machine_devices.h&d=AwIFAg&c=SgMrq23dbjbGX6e0ZsSHgEZX6A4IAf1SO3AJ2bNrHlk&r=vxDfYJYhOaaufTHzA3yxVVn--9Yf3Ig5TrUiTFGL8pc&m=xES3WJjaY0BbvKig8sNNQD6C8RdHjP2OrtyIzDDzCSQ&s=iQYNaJIbR5OLyOVMwKZpK0SV1yoBHcUcOP8jLxlQjog&e= >> >> If the uart device that you are attempting to use is not in the list, >> feel free to add it. >> >> - Alex >> >> >> >> ________________________________________ >> From: Devel [[email protected]] on behalf of Jeff Hieb [ >> [email protected]] >> Sent: Sunday, 27 September 2015 23:07 >> To: [email protected] >> Subject: [seL4] Camkes MMIO Driver Failed to find device frame >> >> I am working on a UART device driver in camkes for AM335x. >> >> When I load the image on the board I get this error: >> >> Creating object frame_drv_group_bin_42 in slot 596, from untyped 1f6... >> device frame, paddr = 0x48022000, size = 12 bits >> >> capDL-loader :: << Error: Failed to find device frame at paddr = >> 0x48022000 >> >> >> >> I am reasonably confident the address is correct, >> ( >> https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_seL4_libplatsupport_blob_master_plat-5Finclude_am335x_platsupport_plat_serial.h-23L15&d=AwIFAg&c=SgMrq23dbjbGX6e0ZsSHgEZX6A4IAf1SO3AJ2bNrHlk&r=vxDfYJYhOaaufTHzA3yxVVn--9Yf3Ig5TrUiTFGL8pc&m=xES3WJjaY0BbvKig8sNNQD6C8RdHjP2OrtyIzDDzCSQ&s=BmKsuwNLcBX2ucG5br_2EA3628PcqbPWzIh-yLbsVM0&e= >> ) >> >> Looking at the source It seems capDL-Loader wants to find this device >> frame in bootinfo >> >> >> https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_seL4_capdl-2Dloader-2Dapp_blob_master_src_main.c-23L731&d=AwIFAg&c=SgMrq23dbjbGX6e0ZsSHgEZX6A4IAf1SO3AJ2bNrHlk&r=vxDfYJYhOaaufTHzA3yxVVn--9Yf3Ig5TrUiTFGL8pc&m=xES3WJjaY0BbvKig8sNNQD6C8RdHjP2OrtyIzDDzCSQ&s=kaspr1EOmJgHcCfdxXCxymmz5b3I4Fuv_cRwAPqOMgI&e= >> >> Any help on how capDL-loader builds bootinfo would be appreciated. >> >> Jeff >> >> -- >> Jeffrey L. Hieb >> Department of Engineering Fundamentals >> University of Louisville >> Louisville Kentucky 40292 >> (502) 852 0465 >> >> >> _______________________________________________ >> Devel mailing list >> [email protected] >> >> https://urldefense.proofpoint.com/v2/url?u=https-3A__sel4.systems_lists_listinfo_devel&d=AwIFAg&c=SgMrq23dbjbGX6e0ZsSHgEZX6A4IAf1SO3AJ2bNrHlk&r=vxDfYJYhOaaufTHzA3yxVVn--9Yf3Ig5TrUiTFGL8pc&m=xES3WJjaY0BbvKig8sNNQD6C8RdHjP2OrtyIzDDzCSQ&s=rKkqGJPIQpRtHhsDyxjrcUE5EBpZ9S3AHoMVeHB707s&e= >> >> ________________________________ >> >> The information in this e-mail may be confidential and subject to legal >> professional privilege and/or copyright. National ICT Australia Limited >> accepts no liability for any damage caused by this email or its attachments. >> > > > _______________________________________________ > Devel mailing list > [email protected] > https://sel4.systems/lists/listinfo/devel > -- Tim Newsham | www.thenewsh.com/~newsham | @newshtwit | thenewsh.blogspot.com
From 01c13c0f67af3a082fe0cc3c14e7aa27a06b5e10 Mon Sep 17 00:00:00 2001 From: Tim Newsham <[email protected]> Date: Sun, 15 Mar 2015 21:07:37 -1000 Subject: [PATCH] - setup clock and enable dmtimer3 on am335x --- include/plat/am335x/plat/machine/devices.h | 8 ++++-- src/plat/am335x/machine/hardware.c | 46 ++++++++++++++++++++++++++++-- 2 files changed, 49 insertions(+), 5 deletions(-) diff --git a/include/plat/am335x/plat/machine/devices.h b/include/plat/am335x/plat/machine/devices.h index adbe875..8c9704e 100644 --- a/include/plat/am335x/plat/machine/devices.h +++ b/include/plat/am335x/plat/machine/devices.h @@ -16,11 +16,12 @@ #define UART0_PPTR 0xfff02000 #define DMTIMER0_PPTR 0xfff03000 #define WDT1_PPTR 0xfff04000 +#define CMPER_PPTR 0xfff05000 /* Other devices on the SoC. */ -#define INTC_PADDR 0x48200000 -#define UART0_PADDR 0x44E09000 +#define INTC_PADDR 0x48200000 +#define UART0_PADDR 0x44E09000 #define DMTIMER0_PADDR 0x44E05000 #define DMTIMER2_PADDR 0x48040000 #define DMTIMER3_PADDR 0x48042000 @@ -28,7 +29,8 @@ #define DMTIMER5_PADDR 0x48046000 #define DMTIMER6_PADDR 0x48048000 #define DMTIMER7_PADDR 0x4804A000 -#define WDT1_PADDR 0x44e35000 +#define WDT1_PADDR 0x44e35000 +#define CMPER_PADDR 0x44e00000 #endif diff --git a/src/plat/am335x/machine/hardware.c b/src/plat/am335x/machine/hardware.c index 41a4eb1..005d2df 100644 --- a/src/plat/am335x/machine/hardware.c +++ b/src/plat/am335x/machine/hardware.c @@ -42,14 +42,15 @@ BOOT_CODE p_region_t get_avail_p_reg(unsigned int i) const p_region_t BOOT_RODATA dev_p_regs[] = { /* SoC devices: */ - { /* .start = */ UART0_PADDR, /* .end = */ UART0_PADDR + (1 << PAGE_BITS) }, + { /* .start = */ UART0_PADDR, /* .end = */ UART0_PADDR + (1 << PAGE_BITS) }, { /* .start = */ DMTIMER2_PADDR, /* .end = */ DMTIMER2_PADDR + (1 << PAGE_BITS) }, { /* .start = */ DMTIMER3_PADDR, /* .end = */ DMTIMER3_PADDR + (1 << PAGE_BITS) }, { /* .start = */ DMTIMER4_PADDR, /* .end = */ DMTIMER4_PADDR + (1 << PAGE_BITS) }, { /* .start = */ DMTIMER5_PADDR, /* .end = */ DMTIMER5_PADDR + (1 << PAGE_BITS) }, { /* .start = */ DMTIMER6_PADDR, /* .end = */ DMTIMER6_PADDR + (1 << PAGE_BITS) }, { /* .start = */ DMTIMER7_PADDR, /* .end = */ DMTIMER7_PADDR + (1 << PAGE_BITS) }, - { /* .start = */ WDT1_PADDR, /* .end = */ WDT1_PADDR + (1 << PAGE_BITS) }, + { /* .start = */ WDT1_PADDR, /* .end = */ WDT1_PADDR + (1 << PAGE_BITS) }, + { /* .start = */ CMPER_PADDR, /* .end = */ CMPER_PADDR + (1 << PAGE_BITS) }, /* Board devices. */ /* TODO: This should ultimately be replaced with a more general solution. */ }; @@ -104,6 +105,18 @@ map_kernel_devices(void) ) ); + /* map kernel device: CMPER */ + map_kernel_frame( + CMPER_PADDR, + CMPER_PPTR, + VMKernelOnly, + vm_attributes_new( + true, /* armExecuteNever */ + false, /* armParityEnabled */ + false /* armPageCacheable */ + ) + ); + #ifdef DEBUG /* map kernel device: UART */ map_kernel_frame( @@ -119,6 +132,13 @@ map_kernel_devices(void) #endif } +#define CMPER_REG(base, off) ((volatile uint32_t *)((base) + (off))) +#define CMPER_TIMER3_CLKCTRL 0x84 +#define CMPER_CLKCTRL_DISABLE 0 +#define CMPER_CLKCTRL_ENABLE 2 +#define CMPER_CLKSEL_TIMER3 0x50c +#define CMPER_CKLSEL_MOSC 1 + #define INTCPS_SYSCONFIG_SOFTRESET BIT(1) #define INTCPS_SYSSTATUS_RESETDONE BIT(0) @@ -295,6 +315,27 @@ disableWatchdog(void) } } +/* + * Enable DMTIMER clocks, otherwise their registers wont be accessible. + * This could be moved out of kernel. + */ +static BOOT_CODE void +enableTimers(void) +{ + uint32_t cmper = CMPER_PPTR; + + /* XXX repeat this for DMTIMER4..7 */ + /* select clock */ + *CMPER_REG(cmper, CMPER_CLKSEL_TIMER3) = CMPER_CKLSEL_MOSC; + while((*CMPER_REG(cmper, CMPER_CLKSEL_TIMER3) & 3) != CMPER_CKLSEL_MOSC) + continue; + + /* enable clock */ + *CMPER_REG(cmper, CMPER_TIMER3_CLKCTRL) = CMPER_CLKCTRL_ENABLE; + while((*CMPER_REG(cmper, CMPER_TIMER3_CLKCTRL) & 3) != CMPER_CLKCTRL_ENABLE) + continue; +} + /* Configure dmtimer0 as kernel preemption timer */ /** DONT_TRANSLATE @@ -305,6 +346,7 @@ initTimer(void) int timeout; disableWatchdog(); + enableTimers(); timer->cfg = TIOCP_CFG_SOFTRESET; -- 1.9.1
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