Hi Neelesh, Communication between PS (the CPU) and PL is generally done through the GP AXI bus. A PL peripheral that is connected to this bus will have an address range associated with it (usually 16KB in size). When the PS reads/writes to an address within this range, the transaction is routed via a hierarchy of interconnects to the appropriate AXI port. Note that a MMU is present on the ARM processor. The address range that is associated with your peripheral may first need to be mapped to an appropriate virtual memory address before it can be accessed.
Fixed peripherals operate in a similar way and hence no special consideration needs to be made when writing the driver for a PL-implemented peripheral. The purpose of the driver is simply to translate a function into the sequence of AXI reads and writes that are required to instruct the peripheral to perform some action. You may want to use an existing drivers as an example: https://github.com/seL4/libplatsupport/blob/master/src/plat/zynq7000/serial.c If you are using Vivado, an AXI peripheral wizard is provided that will create a very simple peripheral for you to start with. The associated address range can be found in the Address Editor. You might find these resources useful: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug940-vivado-tutorial-embedded-design.pdf http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug1118-vivado-creating-packaging-custom-ip.pdf http://www.cse.unsw.edu.au/~cs4601/16s1/labs/custom-ip-lab.pdf - Alex ________________________________________ From: Devel [[email protected]] on behalf of Neelesh Vemula [[email protected]] Sent: Sunday, 7 August 2016 06:40 To: [email protected] Subject: [seL4] on Zynq Hi all, I am completely new with seL4, embedded systems as well as the fpga world. I am working on installing seL4 on Zynq fpga and use it. I have successfully able to boot up a "hello world" application using uboot(sd card bootup) on the zynq device. However, I have no clue as in how to setup communication between the sel4 logic and the PL(fpga fabric). If I am correct some sort of device driver has to be written or is there anything that is inbuilt or someone else who has worked on a similar project. Any guidance in this regard will be utmost helpful. Thanks a ton! Neelesh Vemula ________________________________ The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments. _______________________________________________ Devel mailing list [email protected] https://sel4.systems/lists/listinfo/devel
