Hi,
I am writing a blt funtion to transfer a rectangular area
image data from offscreen to onscreen on ATI Radeon 7500
graphic card. But after lots of tries, I still couldn't
see the image on my screen.:( Can someone help me check
this out ?
>From the blt example code ( for windows) provided by ATI doc,
the major steps include Radeon initialization, reading
image data to (src_x, src_y) in frame buffer, setting bunch
of related registers, and then initiating the blt operation
by setting the initiator register.
The resolution is set to 800x600x8. The following is my code.
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++
/* Initialization */
xres = 800;
yres = 600;
img_bpp = 8;
bytepp = (img_bpp + 1)/8;
pitch = ((xres * bytepp + 0x3f) & ~(0x3f))/64;
byte_pitch = pitch * 64;
... ...
/* copy image data from system memory to src_x, src_y
* rectangular area in frame buffer. Variable dinfo is
* a structure used to save image infomation. Image
* data is saved linearly in system memory.
*/
width = dinfo->img_width[blt_index];
height = dinfo->img_height[blt_index];
src_x = 0;
src_y = 600;
dstaddr = (char *) (agp_dev.vga_base + byte_pitch * src_y + src_x);
srcaddr = (char *) (image_data_base + dinfo->img_offset[blt_index]);
for(i=0; i<height; i++)
{
for(j=0; j<width; j++) {
dstaddr[j] = srcaddr[j];
}
dstaddr += byte_pitch;
srcaddr += width;
}
... ...
/* blt function:
*
* Radeon_WaitForFifo(entry) is used to make sure there are
* enough entries in command fifo.
*/
/* Radeon initialization. */
/* Do I have to initialize some registers here? I think
* the default values should be fine.
*/
dst_x = 20;
dst_y = 30;
Radeon_WaitForFifo (4);
// Tell the engine where the source data resides.
writel((src_y << 16 ) | src_x, agp_dev.reg_base + SRC_Y_X);
// set the mix to a rectangular source
temp = readl(agp_dev.reg_base + DP_MIX);
writel ( 0x00000200|temp, agp_dev.reg_base + DP_MIX);
// Set the drawing direction to left->right, top->bottom
temp = readl(agp_dev.reg_base + DP_CNTL);
writel (0x03|temp, agp_dev.reg_base + DP_CNTL);
// make the src pixel = dst pixel = 8bpp pseudocolor
temp = readl (agp_dev.reg_base + DP_DATATYPE);
writel ( temp|0x00030002 ,agp_dev.reg_base + DP_DATATYPE);
Radeon_WaitForFifo (2);
// set destination x and y values
writel ((dst_y << 16 ) | dst_x, agp_dev.reg_base + DST_Y_X);
// this is the blt initiator.
writel (width | (height << 16 ), agp_dev.reg_base +
DST_HEIGHT_WIDTH);
... ...
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
void Radeon_WaitForFifo (dword entries)
{
while ((readl(agp_dev.reg_base + RBBM_STATUS) & 0x0000007f) <
entries)
{
printk("\nNo enough entries in command FIFO.\n");
}
return;
}
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Questions:
1. Is Radeon_WaitForFifo necessary if there are enough entries
in command fifo?
2. If command fifo full, does that mean I cannot set registers
successfully until needed entries are available?
3. Do I have to set some registers at "Radeon initialization"
step?
4. What's the problem with my code?
Thanks in advance,
jing
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