Christian, > The registers to change are documented in the datasheet of the > specific chipset by Intel. You'll have to look for the PAM registers > (at least that's what they're called for i8xx-chipsets).
That was really helpful. I was surprised to find the datasheets readily available for download from Intel. I downloaded the one for the 915GM and also 855GM, so I could understand the existing 855resolution code better. 915GM: http://www.intel.com/design/mobile/datashts/305264.htm 855GM: http://www.intel.com/design/chipsets/datashts/252615.htm I still don't understand the following code completely (original code for 855GM): // Tell the card which register to write: outl(0x8000005a, 0xcf8); // Send the data: outb(0x33, 0xcfe); Now, the first statement makes sense, kind of. The format is specified in section 4.6.1 (page 56) of the 855GM spec. Writing four bytes to 0xcf8 populates CONFIG_ADDRESS. The value 0x8000005a means: - Enable [31] - Bus 0 [23:16] - Device 0 [15:11] - Function Number 0 [10:8] - Register 0x16 [7:2] Next, Writing is enabled by setting bits 0, 1, 4 and 5, as documented in section 4.8.17 (page 70). In fact, this enables two, not just one PAM register for R/W. But which ones? I don't understand where 0xcfe comes from! CONFIG_DATA starts at 0xcfc (4.6.2., page 57); which of the 14 PAM Registers are we writing to? Table 26 (page 71) lists offsets for the PAMs, but they don't make sense to me. Section 5.4.5 (page 132) seems to cover this, but I don't get it. Also, where does Register 0x16 come from? And last, once I am ready to modify this for 915GM: Which bus and device does my machine use? According to the X log files, it's PCI 00:02:0 - so do I use bus 0, device 2, function number 0? Many questions... I am grateful for any help or other pointers. - Michael -- Michael Jastram - [EMAIL PROTECTED] - http://jastram.de/ PGP: 9301 1A1A 58C6 2433 4EA0 A040 A5AE 4122 12C1 EB80 _______________________________________________ Devel mailing list Devel@XFree86.Org http://XFree86.Org/mailman/listinfo/devel
