> A question though(16-bit/32-bit controllers, e.g. 9118): > > If the device is strapped to 16-bit host bus mode, a single read 32-bit would > reveal us if the bus converts the load 32-bit to two load 16-bit or > not because the D[31:16] data bus lines are left in a high impedance state. > Right ?
Right. > Maybe a pair of reads - same address - is safer, the controller invalidate > the read (what does it mean in terms of bytes read ?) if it samples the same > address (load 32 not split in 16-bit loads) on consecutive reads. > If the conversion is correct the smsc returns the BYTE_TEST value otherwise > we would notice the problem. If the device is strapped for 16-bit we must ALWAYS read or write in pairs. Actually, one of the two reads is *supposed* to have A[1] set and one is supposed to have it cleared to read the two halves. The data sheet says that reading the same 16-bit word twice gives invalid results but is not fatal. > I can write the code in the DT port context, but I do not have any > 16-bit strapped smsc lan controller at hand, so I cannot test it, but I can post > the patch for review and testing on the list. Quite a few device variants are 16-bit only (e.g. 9221), so there are plenty out there. _______________________________________________ devicetree-discuss mailing list [email protected] https://lists.ozlabs.org/listinfo/devicetree-discuss
