Grant, Anton, reading through the of/gpio docs and thinking about some improvements for our proprietary "ancient" code gives a lot of opportunities for major improvements ... since you are authors and your quick help in the past is really appreciated I dare to address you directly ;-)
On some (mostly PowerPC) based boards we have NAND-Flash connected to a PCI FPGA. There's no NAND controller inside ... just bitbang. Currently there's an implementation using "struct nand_chip" + hooks + nand_scan() inside the pci driver. Since the driver is designed to do other things and is not available during boot (=no RFS on Nand) I definitely want to get rid of this. To me it looks like we could use the "gpio-nand" driver. All we need is registering the proper (mem mapped) GPIOs with the required names via device-tree. As far as I understand the FPGA can be considered an of_mm_gpio_chip ? Honestly I don't know how to define it using dts syntax. All we have regarding PCI is general bus ranges, devsel and irq lines ... and of course the offset inside the FPGA. I've not seen a direct representation of a PCI device - only SoC components. How am I supposed to handle the unknown (=dynamically assigned) base address ? Since the system also has PCI slots I can't make sure to always get the same adress ... Can you give some hints/advice how to define the FPGA as a GPIO-Controller ? Regards, André MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
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