On Fri, Jan 13, 2012 at 08:30:30PM -0800, Turquette, Mike wrote: ... > I had envisioned fixed clocks as being clocks whose rates could never > change; obviously this is mostly useful for root clocks like > oscillators and whatnot. > > There is nothing wrong with using fixed clock for sgtl5000-sys-mclk, > but it's rate *can* change if it's parent rate ever changes. This may > be very unlikely on your platform, in which case again it is OK to use > fixed clock here if you want to. > > However... I'm inclined to say that sgtl5000-sys-mclk is good > candidate for a dummy clock: it follows it's parent rate, doesn't > gate, doesn't divide it's parent rate, only has one input. There > isn't a common dummy clock in the v4 patches, but there is in v5. The > key difference between the fixed rate clock and the dummy clock is > that the dummy clock looks at clk->parent->rate in it's .get_rate, > whereas a fixed rate clock will have it's rate cached in struct > clk_fixed. > > Thoughts? > I would say this modeling looks all sane to me, except both the fixed-clock soc-26m-clk and dummy-clock sgtl5000-sys-mclk in this case have a gate which is controlled by gpio.
-- Regards, Shawn _______________________________________________ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss