On Wed, Aug 15, 2012 at 08:25:25PM +0000, Arnd Bergmann wrote: > On Wednesday 15 August 2012, Thierry Reding wrote: > > Yes, that was my understanding as well. So currently I haven't seen any > > problems with this because I only use one of the two host bridges. But I > > suppose I should add code to initialize the bus number aperture properly > > either via platform device resources (for the non-DT case) and the > > device tree otherwise. > > I think when we last discussed this, the assumption was that each > root port has its own config space range and its own pci domain, > so you don't have to worry about bus apertures because each root port > can then have all 255 bus numbers. Has that turned out to be incorrect > now?
At least for the config space this is incorrect. There's a single region to access the configuration space for all devices below the PCIe controller. So it is shared by both (Tegra20) or all three (Tegra30) root ports. I'm not sure about PCI domains. Do you have any good pointers as to where I could read up on them? If they need special hardware support, then I think Tegra doesn't support them either. At least I haven't come across any mention of domains while going through the, admittedly some- what sparse on PCIe, Tegra documentation. Thierry
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