On Tue, 18 Dec 2012 12:29:53 +0530 Laxman Dewangan <ldewan...@nvidia.com> wrote:
> Nvidia's Tegra has multiple uart controller which supports: > - APB dma based controller fifo read/write. > - End Of Data interrupt in incoming data to know whether end > of frame achieve or not. > - Hw controlled RTS and CTS flow control to reduce SW overhead. > > Add serial driver to use all above feature. > > Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> Acked-by: Alan Cox <a...@linux.intel.com> _______________________________________________ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
