Rob Herring <robherri...@gmail.com> wrote @ Mon, 17 Dec 2012 15:00:46 +0100:
> On 12/17/2012 12:18 AM, Hiroshi Doyu wrote:
> > Set Snoop Control Unit(SCU) register base address dynamically from DT.
> >
> > Signed-off-by: Hiroshi Doyu <hd...@nvidia.com>
> > ---
> > arch/arm/mach-tegra/platsmp.c | 23 ++++++++++++++++++++---
> > 1 file changed, 20 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
> > index 1b926df..45c0b79 100644
> > --- a/arch/arm/mach-tegra/platsmp.c
> > +++ b/arch/arm/mach-tegra/platsmp.c
> > @@ -18,6 +18,8 @@
> > #include <linux/jiffies.h>
> > #include <linux/smp.h>
> > #include <linux/io.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> >
> > #include <asm/cacheflush.h>
> > #include <asm/hardware/gic.h>
> > @@ -36,7 +38,7 @@
> >
> > extern void tegra_secondary_startup(void);
> >
> > -static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
> > +static void __iomem *scu_base;
> >
> > #define EVP_CPU_RESET_VECTOR \
> > (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
> > @@ -143,14 +145,28 @@ done:
> > return status;
> > }
> >
> > +static const struct of_device_id cortex_a9_scu_match[] __initconst = {
> > + { .compatible = "arm,cortex-a9-scu", },
> > + {}
> > +};
> > +
> > /*
> > * Initialise the CPU possible map early - this describes the CPUs
> > * which may be present or become present in the system.
> > */
> > static void __init tegra_smp_init_cpus(void)
> > {
> > - unsigned int i, ncores = scu_get_core_count(scu_base);
> > + struct device_node *np;
> > + unsigned int i, ncores = 1;
> > +
> > + np = of_find_matching_node(NULL, cortex_a9_scu_match);
> > + if (!np)
> > + return;
> > + scu_base = of_iomap(np, 0);
>
> Did you actually test this? Unless something changed, ioremap does not
> work this early. The only reason to have it mapped this early is to get
> the core count, but that doesn't work on A15 or A7. So we really need to
> get core count/mask in a standard way. At least some work to get core
> count from DT went into 3.8.
>
> BTW, you can get the scu address on the A9 by reading cp15 register:
>
> /* Get SCU base */
> asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
>
> It's still probably good to have the DT node, but the reg property can
> be optional in this case.
>
> We need to move away from having the DT matching code within the
> platforms. This should all be moved to the scu code in a scu_of_init
> function that could be called from common code.
If we can get SCU base address from CP15, do we still need SCU entry
in DT? If not, the following would be the only API to get SCU base?
>From 9bbecb50759f39d9c762977145407ea4f8a4d5ac Mon Sep 17 00:00:00 2001
From: Hiroshi Doyu <hd...@nvidia.com>
Date: Mon, 14 Jan 2013 12:35:33 +0200
Subject: [PATCH 1/1] ARM: Add API to detect SCU base address from CP15
Add API to detect SCU base address from CP15.
Signed-off-by: Hiroshi Doyu <hd...@nvidia.com>
---
arch/arm/include/asm/smp_scu.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 4eb6d00..6015ede 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -6,6 +6,20 @@
#define SCU_PM_POWEROFF 3
#ifndef __ASSEMBLER__
+static inline phys_addr_t scu_get_base(void)
+{
+ phys_addr_t pa;
+ unsigned long part_number = read_cpuid_part_number();
+
+ switch (part_number) {
+ case ARM_CPU_PART_CORTEX_A9:
+ /* Get SCU physical base */
+ asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
+ return pa;
+ default:
+ return 0;
+ }
+}
unsigned int scu_get_core_count(void __iomem *);
void scu_enable(void __iomem *);
int scu_power_mode(void __iomem *, unsigned int);
--
1.7.9.5
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