From: Gerlando Falauto <gerlando.fala...@keymile.com>
There are cases where all irq_chip_type instances have separate mask
registers, making a shared mask register cache unsuitable for the
purpose.
Introduce a new flag IRQ_GC_MASK_CACHE_PER_TYPE. If set, point the per
chip mask pointer to the per chip private mask cache instead.
[ tglx: Simplified code, renamed flag and massaged changelog ]
Signed-off-by: Gerlando Falauto <gerlando.fala...@keymile.com>
Cc: Lennert Buytenhek <ker...@wantstofly.org>
Cc: Simon Guinot <si...@sequanux.org>
Cc: Joey Oravec <jora...@drewtech.com>
Cc: Ben Dooks <ben-li...@fluff.org>
Cc: Nicolas Pitre <n...@fluxnic.net>
Cc: Jason Cooper <ja...@lakedaemon.net>
Cc: Andrew Lunn <and...@lunn.ch>
Cc: Holger Brunck <holger.bru...@keymile.com>
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Thomas Gleixner <t...@linutronix.de>
---
include/linux/irq.h | 2 ++
kernel/irq/generic-chip.c | 17 ++++++++++-------
2 files changed, 12 insertions(+), 7 deletions(-)
Index: linux-2.6/include/linux/irq.h
===================================================================
--- linux-2.6.orig/include/linux/irq.h
+++ linux-2.6/include/linux/irq.h
@@ -704,10 +704,12 @@ struct irq_chip_generic {
* @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
* irq chips which need to call irq_set_wake() on
* the parent irq. Usually GPIO implementations
+ * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
*/
enum irq_gc_flags {
IRQ_GC_INIT_MASK_CACHE = 1 << 0,
IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
+ IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
};
/* Generic chip callback functions */
Index: linux-2.6/kernel/irq/generic-chip.c
===================================================================
--- linux-2.6.orig/kernel/irq/generic-chip.c
+++ linux-2.6/kernel/irq/generic-chip.c
@@ -241,18 +241,21 @@ void irq_setup_generic_chip(struct irq_c
{
struct irq_chip_type *ct = gc->chip_types;
unsigned int i;
+ u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
raw_spin_lock(&gc_lock);
list_add_tail(&gc->list, &gc_list);
raw_spin_unlock(&gc_lock);
- /* Init mask cache ? */
- if (flags & IRQ_GC_INIT_MASK_CACHE)
- gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
-
- /* Initialize mask cache pointer */
- for (i = 0; i < gc->num_ct; i++)
- ct[i].mask_cache = &gc->mask_cache;
+ for (i = 0; i < gc->num_ct; i++) {
+ if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
+ mskptr = &ct[i].mask_cache_priv;
+ mskreg = ct[i].regs.mask;
+ }
+ ct[i].mask_cache = mskptr;
+ if (flags & IRQ_GC_INIT_MASK_CACHE)
+ *mskptr = irq_reg_readl(gc->reg_base + mskreg);
+ }
for (i = gc->irq_base; msk; msk >>= 1, i++) {
if (!(msk & 0x01))
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