On Tuesday 18 June 2013, Thomas Petazzoni wrote: > > To clarify my earlier comment, I think it would be nicer to write this as > > > > ranges = > > <0x82000000 0 0x40000 0xffff0001 0x40000 0 > > 0x00002000 > > 0x82000000 0 0x80000 0xffff0001 0x80000 0 > > 0x00002000 > > 0x82000000 1 0 MBUS_ID(0x12, 0x34) 0 1 0 > > 0x82000000 2 0 MBUS_ID(0x13, 0x34) 0 1 0 > > 0x81000000 1 0 MBUS_ID(0x12, 0x35) 0 0 > > 0x10000; > > 0x81000000 2 0 MBUS_ID(0x13, 0x35) 0 0 > > 0x10000>; > > > > The MBUS_ID numbers above are made up since I don't know them, but this way > > you can > > describe how the entire 4GB MMIO address space of the PCI bus is mapped > > into the > > MBUS address space. > > This is NOT possible because we don't know in advance how much memory > space and I/O space each PCIe device will require. > > Arnd, we've discussed this at length with you while getting the PCIe > driver merged, and we've explained this to you numerous times. Could > you please understand that any of your proposal that suggests writing > down static windows for PCIe devices will not work?
Where did I suggest static windows for PCIe devices? Arnd _______________________________________________ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss