Hi Gerlando,
On Wed, Jul 17, 2013 at 08:35:38AM +0200, Gerlando Falauto wrote:
> On 07/16/2013 02:56 PM, Ezequiel Garcia wrote:
> [...]
> > Also, speaking of "device bus" this nand node should be behind a devicebus
> > node.
> >
> > ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 /*
> > internal-regs */
> > MBUS_ID(0x01, 0x2f) 0 0 0xf4000000 0x400>;
> >
> > devbus {
> > status = "okay";
> > ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x400>;
> >
> > /* nand */
> > nand {
> > compatible = "marvell,orion-nand";
> > reg = <0 0x400>;
> > };
> > };
> >
> > (notice this will allow you to relocate the base address of the NAND windows
> > easily if it conflicts with your PCIe needs).
>
> I am MAYBE slowly starting to understand this whole mbus rework.
> Just one remark though: don't you think it would make sense to add
> something like:
>
> #define MBUS_ID_INTERNAL_REGS MBUS_ID(0xf0, 0x01)
> #define MBUS_ID_NAND MBUS_ID(0x01, 0x2f)
>
Yeah, maybe it would make sense. This has been discussed in the past
and others were against, so that's the reason it's not included in
the series I submitted.
But feel free to send a patch proposing it once the MBus is merged!
Thanks,
--
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
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