On Thursday 30 January 2014, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Patrice CHOTARD wrote:
> > From: Alexandre TORGUE <alexandre.tor...@st.com>
> >
> > This patch adds support to STiD127 SoC.
> > The main adaptation is the L2 cache way size compare to STiH41x SoCs.
> >
> > Signed-off-by: alexandre torgue <alexandre.tor...@st.com>
> > Signed-off-by: Patrice Chotard <patrice.chot...@st.com>
> > ---
> > arch/arm/mach-sti/board-dt.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
>
> Wouldn't it be better to read this value from the l2 cache
> controller node? I'd assume there might be more SoCs that
> will need a similar change, so it's better to come up with
> a solution that doesn't involve changing the kernel every
> time.
Actually reading the code in this file shows that the L2 cache
initialization is the only nonstandard thing in there. We should
really find a way to get rid of the entire function.
Sorry if I missed the initial review, but can you explain
why this is needed to start with?
Arnd
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