On 04/02/2014 04:46 PM, Peter Ujfalusi wrote:
The correct bit is 24 for AHCLKX.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
Yes, thats a clear bug in the data.
Acked-by: Tero Kristo <t-kri...@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e96da9a898ad..cfb8fc753f50 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1640,7 +1640,7 @@
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>,
<&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <28>;
+ ti,bit-shift = <24>;
reg = <0x1860>;
};
--
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