From: Thor Thayer <ttha...@altera.com>
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
Signed-off-by: Thor Thayer <ttha...@altera.com>
To: Rob Herring <robherri...@gmail.com>
To: Pawel Moll <pawel.m...@arm.com>
To: Mark Rutland <mark.rutl...@arm.com>
To: Ian Campbell <ijc+devicet...@hellion.org.uk>
To: Kumar Gala <ga...@codeaurora.org>
To: Rob Landley <r...@landley.net>
To: Russell King <li...@arm.linux.org.uk>
To: Dinh Nguyen <dingu...@altera.com>
Cc: devicetree@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
---
.../bindings/arm/altera/socfpga-sdram.txt | 14 ++++++++++++++
arch/arm/boot/dts/socfpga.dtsi | 5 +++++
2 files changed, 19 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 0000000..525cb76
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
@@ -0,0 +1,14 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl", "syscon";
+ Note that syscon is invoked for this device to support the FPGA
+ bridge driver, EDAC driver and other devices that share the
+ registers.
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+ sdrctl@ffc25000 {
+ compatible = "altr,sdr-ctl", "syscon";
+ reg = <0xffc25000 0x1000>;
+ };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index df43702..6ce912e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -676,6 +676,11 @@
clocks = <&l4_sp_clk>;
};
+ sdrctl@ffc25000 {
+ compatible = "altr,sdr-ctl", "syscon";
+ reg = <0xffc25000 0x1000>;
+ };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
--
1.7.9.5
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