Hi!
> From: Thor Thayer <ttha...@altera.com>
>
> Added EDAC support for reporting ECC errors of CycloneV
> and ArriaV SDRAM controller.
> - The SDRAM Controller registers are used by the FPGA bridge so
> these are accessed through the syscon interface.
> - The configuration of the SDRAM memory size for the EDAC framework
> is discovered from the SDRAM Controller registers.
> - Documentation of the bindings in devicetree/bindings/arm/altera/
> socfpga-sdram-edac.txt
> - Correction of single bit errors, detection of double bit errors.
>
> ---
> v2: Use the SDRAM controller registers to calculate memory size
> instead of the Device Tree. Update To & Cc list. Add maintainer
> information.
I'd reduce number of *s in the messages, otherwise
Reviewed-by: Pavel Machek <pa...@ucw.cz>
for whole series.
Pavel
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