From: Thor Thayer <ttha...@opensource.altera.com>
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>
---
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
v5: No Change, bump version for consistency.
v6: Only map the ctrlcfg register as syscon.
v7: No change. Bump for consistency.
v8: No change. Bump for consistency.
v9: Changes to support a MFD SDRAM controller with nested EDAC.
v10: Revert to using syscon based on feedback.
---
.../bindings/arm/altera/socfpga-sdram-edac.txt | 15 +++++++++++++++
arch/arm/boot/dts/socfpga.dtsi | 11 +++++++++++
2 files changed, 26 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
diff --git
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 0000000..d0ce01d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,15 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+The EDAC accesses a range of registers in the SDRAM controller.
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- altr,sdr-syscon : phandle of the sdr module
+- interrupts : Should contain the SDRAM ECC IRQ in the
+ appropriate format for the IRQ controller.
+
+Example:
+ sdramedac {
+ compatible = "altr,sdram-edac";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <0 39 4>;
+ };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4676f25..45b361e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -603,6 +603,17 @@
};
};
+ sdr: sdr@ffc25000 {
+ compatible = "syscon";
+ reg = <0xffc25000 0x1000>;
+ };
+
+ sdramedac {
+ compatible = "altr,sdram-edac";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <0 39 4>;
+ };
+
L2: l2-cache@fffef000 {
compatible = "arm,pl310-cache";
reg = <0xfffef000 0x1000>;
--
1.7.9.5
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