>-----Original Message-----
>From: Shawn Guo [mailto:[email protected]]
>Sent: Sunday, October 19, 2014 9:37 AM
>To: Lu Jingchang-B35083
>Cc: [email protected]; [email protected]; linux-arm-
>[email protected]; [email protected]; Lu Jingchang-
>B35083; Badola Nikhil-B46172; Zhao Chenhui-B35336; Gupta Suresh-B42813;
>Leekha Shaveta-B20052; Gupta Ruchika-R66431; Sharma Bhupesh-B45370; Fu
>Chao-B44548; Xiubo Li-B47053
>Subject: Re: [PATCHv5 1/6] ARM: dts: Add SoC level device tree support for
>LS1021A
>
>On Mon, Oct 13, 2014 at 05:35:58PM +0800, Jingchang Lu wrote:
>> +/ {
>> +    compatible = "fsl,ls1021a";
>> +    interrupt-parent = <&gic>;
>> +
>> +    aliases {
>> +            serial0 = &lpuart0;
>> +            serial1 = &lpuart1;
>> +            serial2 = &lpuart2;
>> +            serial3 = &lpuart3;
>> +            serial4 = &lpuart4;
>> +            serial5 = &lpuart5;
>> +            sysclk = &sysclk;
>
>What is this sysclk aliase used for?
The sysclk alias is used by dtb fixup stage in u-boot to set the proper clk 
frequency
for its configurable. The sysclk is compatible to "fixed-clock" but there may 
be more
than one "fixed-clock" source and only the sysclk is desired, so an alias is 
add to
located it exclusively. Thanks.

>
>> +            };
>
>Bad indent.
>
>> +
>> +    cpus {
>> +            #address-cells = <1>;
>> +            #size-cells = <0>;
>> +
>> +            cpu@f00 {
>> +                    compatible = "arm,cortex-a7";
>> +                    device_type = "cpu";
>> +                    reg = <0xf00>;
>> +            };
>> +
>> +            cpu@f01 {
>> +                    compatible = "arm,cortex-a7";
>> +                    device_type = "cpu";
>> +                    reg = <0xf01>;
>> +            };
>> +    };
>> +
>> +    timer {
>> +            compatible = "arm,armv7-timer";
>> +            interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
>IRQ_TYPE_LEVEL_LOW)>,
>> +                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
>IRQ_TYPE_LEVEL_LOW)>,
>> +                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
>IRQ_TYPE_LEVEL_LOW)>,
>> +                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
>IRQ_TYPE_LEVEL_LOW)>;
>
>I like this indent style ...
>
>> +    };
>> +
>> +    pmu {
>> +            compatible = "arm,cortex-a7-pmu";
>> +            interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
>> +                            <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
>
>... not this style.  Please fix such indents through the file.

I will, thanks.

Best Regards,
Jingchang

>
>> +    };
>
>Shawn
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