Signed-off-by: Flora Fu <flora...@mediatek.com>
---
 Documentation/devicetree/bindings/mfd/mt6397.txt | 75 ++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/mt6397.txt

diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt 
b/Documentation/devicetree/bindings/mfd/mt6397.txt
new file mode 100644
index 0000000..64ef408
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -0,0 +1,75 @@
+MediaTek MT6397 Multifunction Device Driver
+
+MT6397 is a multifunction device with the following sub modules:
+- Regulator
+- RTC
+- Audio codec
+- GPIO
+- Clock
+
+It is interfaced to host controller using SPI interface by a proprietary 
hardware
+called PMIC wrapper or pwrap. MT6397 MFD is a child device of pwrap.
+See the following for pwarp node definitions:
+Documentation/devicetree/bindings/soc/mediatek,mt8135-pwrap.txt
+
+This document describes the binding for mfd device and its sub module.
+
+Required properties:
+compatible: "mediatek,mt6397"
+
+Optional properties:
+- codec: Audio codec
+- pinctrl: GPIO in mt6397
+- rtc: RTC
+- clock: clocks in mt6397
+- regulators: regulators in mt6397
+
+Example:
+       pwrap: pwrap@1000f000 {
+               compatible = "mediatek,mt8135-pwrap";
+               reg = <0 0x1000f000 0 0x1000>,
+                       <0 0x11017000 0 0x1000>;
+               reg-names = "pwrap-base", "pwrap-bridge-base";
+               interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+               resets = <&infrarst MT8135_INFRA_PMIC_WRAP_RST>,
+                               <&perirst MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+               reset-names = "infra-pwrap-rst",
+                               "peri-pwrap-bridge-rst";
+               clocks = <&pmicspi_sel>, <&clk26m>;
+               clock-names = "pmicspi-sel", "pmicspi-parent";
+
+               pmic {
+                       compatible = "mediatek,mt6397";
+
+                       codec: mt6397codec {
+                               compatible = "mediatek,mt6397-codec";
+                       };
+
+                       pinctrl@0x0000C000 {
+                               compatible = "mediatek,mt6397-pinctrl";
+                               reg = <0 0x0000C000 0 0x0108>;
+                               gpio-controller;
+                       };
+
+                       mt6397regulator: mt6397regulator {
+                               compatible = "mediatek,mt6397-regulator";
+
+                               mt6397_vpca15_reg: buck_vpca15 {
+                                       regulator-compatible = "buck_vpca15";
+                                       regulator-name = "vpca15";
+                                       regulator-min-microvolt = < 850000>;
+                                       regulator-max-microvolt = <1400000>;
+                                       regulator-ramp-delay = <12500>;
+                                       regulator-always-on;
+                               };
+
+                               mt6397_vgp4_reg: ldo_vgp4 {
+                                       regulator-compatible = "ldo_vgp4";
+                                       regulator-name = "vgp4";
+                                       regulator-min-microvolt = <1200000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       regulator-enable-ramp-delay = <218>;
+                               };
+                       };
+               };
+       };
-- 
1.8.1.1.dirty

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