2015-08-19 14:45 GMT+09:00 Masahiro Yamada <yamada.masah...@socionext.com>: > This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings > says that the bits[15:8] of the 3rd cell of the interrupts property > represents PPI interrupt CPU mask. Because the timer interrupts are > wired to all of the 4 cores, bits[15:8] should be set to 0xf. > > Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
This has been superseded by v2. -- Best Regards Masahiro Yamada -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
