Hi Gabriel, On 08/24/2015 11:40 AM, Gabriel Fernandez wrote:
This patch configure correctly the MMC-0 clock for STiH418 platform.Signed-off-by: Gabriel Fernandez <gabriel.fernan...@linaro.org> --- arch/arm/boot/dts/stih418-b2199.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index 82eee39..7a03ca6 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -85,6 +85,10 @@ sd-uhs-sdr50; sd-uhs-sdr104; sd-uhs-ddr50; + + assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>; + assigned-clock-parents = <&clk_s_c0_pll1 0>; + assigned-clock-rates = <200000000>;
Thanks for the fix, but I would rather define the parent and rate in the SoC dtsi file, i.e. stih418.dtsi.
If you agree to change, you can add: Acked-by: Maxime Coquelin <maxime.coque...@st.com> Thanks! Maxime -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
