On Thu, Nov 19, 2015 at 11:35:23AM +0800, Chris Zhong wrote:
> From: Liu Ying <ying....@freescale.com>
>
> This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
> host controller DRM bridge driver.
>
> Signed-off-by: Liu Ying <ying....@freescale.com>
> Signed-off-by: Chris Zhong <z...@rock-chips.com>
>
> ---
>
> Changes in v3:
> move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge
>
> Changes in v2: None
>
> .../bindings/display/bridge/dw_mipi_dsi.txt | 76
> ++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
> b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
> new file mode 100644
> index 0000000..0e5c140
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
> @@ -0,0 +1,76 @@
> +Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller
> +
> +The controller is a digital core that implements all protocol functions
> +defined in the MIPI DSI specification, providing an interface between
> +the system and the MIPI DPHY, and allowing communication with a MIPI DSI
> +compliant display.
> +
> +Required properties:
> + - #address-cells: Should be <1>.
> + - #size-cells: Should be <0>.
> + - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi"
> + for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific
> + device tree binding documentations. A common compatible string
> + "snps,dw-mipi-dsi" should be appended for all SoCs.
> + - reg: Represent the physical address range of the controller.
> + - interrupts: Represent the controller's interrupt to the CPU(s).
> + - clocks, clock-names: Phandles to the controller's pll reference
> + clock(ref), configuration clock(cfg) and APB clock(pclk), as
> + described in [1].
You are missing the gpr property.
> +
> +For more required properties, please refer to relevant device tree binding
> +documentations which describe the controller embedded in specific SoCs.
> +
> +Required sub-nodes:
> + - A node to represent a DSI peripheral as described in [2].
Please describe the ports.
> +
> +For more required sub-nodes, please refer to relevant device tree binding
> +documentations which describe the controller embedded in specific SoCs.
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +[2] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
> +
> +example:
> + gpr: iomuxc-gpr@020e0000 {
> + /* ... */
> + };
> +
> + mipi_dsi: mipi@021e0000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
> + reg = <0x021e0000 0x4000>;
> + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
> + gpr = <&gpr>;
> + clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
> + <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
> + <&clks IMX6QDL_CLK_MIPI_IPG>;
> + clock-names = "ref", "cfg", "pclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + mipi_mux_0: endpoint {
> + remote-endpoint = <&ipu1_di0_mipi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mipi_mux_1: endpoint {
> + remote-endpoint = <&ipu1_di1_mipi>;
> + };
> + };
> + };
> +
> + panel {
> + compatible = "truly,tft480800-16-e-dsi";
> + reg = <0>;
> + /* ... */
> + };
> + };
> --
> 2.6.3
>
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