Add Juno cpu capacity bindings information.

Cc: Rob Herring <robh...@kernel.org>
Cc: Pawel Moll <pawel.m...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Ian Campbell <ijc+devicet...@hellion.org.uk>
Cc: Kumar Gala <ga...@codeaurora.org>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Cc: Liviu Dudau <liviu.du...@arm.com>
Cc: Sudeep Holla <sudeep.ho...@arm.com>
Cc: Arnd Bergmann <a...@arndb.de>
Cc: Jon Medhurst <t...@linaro.org>
Cc: Olof Johansson <o...@lixom.net>
Cc: Robin Murphy <robin.mur...@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Juri Lelli <juri.le...@arm.com>
---
 arch/arm64/boot/dts/arm/juno.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index d7cbdd4..06f6d2b 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -33,6 +33,7 @@
        cpus {
                #address-cells = <2>;
                #size-cells = <0>;
+               capacity-scale = <1024>;
 
                A57_0: cpu@0 {
                        compatible = "arm,cortex-a57","arm,armv8";
@@ -40,6 +41,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A57_L2>;
+                       capacity = <1024>;
                };
 
                A57_1: cpu@1 {
@@ -48,6 +50,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A57_L2>;
+                       capacity = <1024>;
                };
 
                A53_0: cpu@100 {
@@ -56,6 +59,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       capacity = <447>;
                };
 
                A53_1: cpu@101 {
@@ -64,6 +68,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       capacity = <447>;
                };
 
                A53_2: cpu@102 {
@@ -72,6 +77,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       capacity = <447>;
                };
 
                A53_3: cpu@103 {
@@ -80,6 +86,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       capacity = <447>;
                };
 
                A57_L2: l2-cache0 {
-- 
2.2.2

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