On Tuesday, 4 February 2014 at 21:02:37 UTC, deadalnix wrote:
Core can share a cache line in read mode, but can't in write mode. That mean that updating the reference count will cause contention on the cache line (core will have to fight for the cache line ownership). That is why immutability + GC is so efficient in a highly concurrent system, and ref counting would ruin that.
Just curious, maybe I got it a bit wrong in my previous reply. It is indeed possible to set the memory type on some CPUs such that you don't get a penalty using some special MTRR (memory type range registers). If the memory type is write-back (regular memory) you get a 43 cycle latency if the cache line might be in multiple local caches and is not dirty (read), 60+ cycle latency if it is dirty (write), and 20-30 cycles latency on local miss, but L3 hit. (if I got that right) But does D actually make sure that immutable types sit in non-write-back memory marked by MTRR?
