gemini-code-assist[bot] commented on PR #18771: URL: https://github.com/apache/tvm/pull/18771#issuecomment-3894470364
## Summary of Changes Hello @tqchen, I'm Gemini Code Assist[^1]! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed! This pull request undertakes a substantial refactoring effort within the TVM Tensor IR (TIR) framework. Its primary goal is to streamline the `tir` namespace by relocating a suite of transformation passes to the more specialized `s_tir` namespace. This strategic move ensures that the core `tir` namespace remains focused on essential, deterministic passes vital for low-level code generation, while allowing `s_tir` to house more advanced or target-specific optimizations. The changes span across C++ implementations, Python bindings, and various integration points, ensuring a clean separation and proper functionality of the migrated passes. ### Highlights * **Namespace Migration**: Migrated a significant number of TIR transformation passes from the `tvm::tir::transform` namespace to the `tvm::s_tir::transform` namespace in C++ source and header files. * **Python Bindings and Usage Updates**: Updated Python FFI bindings for the migrated passes and adjusted their usage in Python pipelines (e.g., Adreno pipeline) and test files to reflect the new `s_tir.transform` module. * **Codebase Reorganization**: Renamed numerous C++ source, header, and Python test files to align with the `s_tir` namespace, ensuring consistent code organization. 🧠**New Feature in Public Preview:** You can now enable **Memory** to help **Gemini Code Assist** learn from your team's feedback. This makes future code reviews more consistent and personalized to your project's style. **Click [here](https://codeassist.google/code-review/login) to enable Memory in your admin console.** <details> <summary><b>Changelog</b></summary> * **include/tvm/s_tir/transform.h** * Added declarations for HoistIfThenElse, HoistExpression, RenormalizeSplitPattern, RewriteUnsafeSelect, InstrumentBoundCheckers, InjectPTXLDG32, InstrumentProfileIntrinsics, LowerVtcmAlloc, ThreadSync, InferFragment, LowerThreadAllreduce, LowerAsyncDMA, InjectPTXAsyncCopy, and MergeSharedMemoryAllocations passes. * **python/tvm/s_tir/backend/adreno/pipeline.py** * Updated calls to LowerAsyncDMA, HoistIfThenElse, RenormalizeSplitPattern, RewriteUnsafeSelect, InstrumentBoundCheckers, InjectPTXLDG32, InstrumentProfileIntrinsics, VerifyVTCMLimit, LowerVtcmAlloc, ThreadSync, InferFragment, LowerThreadAllreduce, InjectPTXAsyncCopy, and MergeSharedMemoryAllocations to use the `s_tir.transform` namespace. * **python/tvm/s_tir/pipeline.py** * Updated calls to LowerAsyncDMA, HoistIfThenElse, RenormalizeSplitPattern, RewriteUnsafeSelect, InstrumentBoundCheckers, InjectPTXLDG32, InstrumentProfileIntrinsics, VerifyVTCMLimit, LowerVtcmAlloc, ThreadSync, InferFragment, LowerThreadAllreduce, InjectPTXAsyncCopy, and MergeSharedMemoryAllocations to use the `s_tir.transform` namespace. * **python/tvm/s_tir/transform/transform.py** * Added Python FFI bindings for HoistIfThenElse, RenormalizeSplitPattern, RewriteUnsafeSelect, InstrumentBoundCheckers, InjectPTXLDG32, InstrumentProfileIntrinsics, VerifyVTCMLimit, LowerVtcmAlloc, ThreadSync, InferFragment, LowerThreadAllreduce, LowerAsyncDMA, InjectPTXAsyncCopy, and MergeSharedMemoryAllocations. * **src/s_tir/analysis/calculate_allocated_memory.cc** * Renamed from `src/tir/analysis/calculate_allocated_memory.cc`. * Updated the pass name registration to `s_tir.VerifyVTCMLimit`. * Added FFI registration for `s_tir.transform.VerifyVTCMLimit`. * **src/s_tir/meta_schedule/postproc/verify_gpu_code.cc** * Updated the call to `MergeSharedMemoryAllocations` from `tir::transform` to `s_tir::transform`. * **src/s_tir/transform/bound_checker.cc** * Renamed from `src/tir/transform/bound_checker.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.InstrumentBoundCheckers`. * **src/s_tir/transform/hoist_expression.cc** * Renamed from `src/tir/transform/hoist_expression.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass config options and FFI registrations for `HoistExpression` and `HoistIfThenElse` to use `s_tir` prefix. * **src/s_tir/transform/inject_ptx_async_copy.cc** * Renamed from `src/tir/transform/inject_ptx_async_copy.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.InjectPTXAsyncCopy`. * **src/s_tir/transform/inject_ptx_ldg32.cc** * Renamed from `src/tir/transform/inject_ptx_ldg32.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.InjectPTXLDG32`. * **src/s_tir/transform/lower_async_dma.cc** * Renamed from `src/tir/transform/lower_async_dma.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.LowerAsyncDMA`. * **src/s_tir/transform/lower_thread_allreduce.cc** * Renamed from `src/tir/transform/lower_thread_allreduce.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.LowerThreadAllreduce`. * **src/s_tir/transform/lower_vtcm_alloc.cc** * Renamed from `src/tir/transform/lower_vtcm_alloc.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.LowerVtcmAlloc`. * **src/s_tir/transform/merge_shared_memory_allocations.cc** * Renamed from `src/tir/transform/merge_shared_memory_allocations.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.MergeSharedMemoryAllocations`. * **src/s_tir/transform/profile_instrumentation.cc** * Renamed from `src/tir/transform/profile_instrumentation.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.InstrumentProfileIntrinsics`. * **src/s_tir/transform/renormalize_split_pattern.cc** * Renamed from `src/tir/transform/renormalize_split_pattern.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.RenormalizeSplitPattern`. * **src/s_tir/transform/rewrite_unsafe_select.cc** * Renamed from `src/tir/transform/rewrite_unsafe_select.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.RewriteUnsafeSelect`. * **src/s_tir/transform/storage_access.cc** * Renamed from `src/tir/transform/storage_access.cc`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * **src/s_tir/transform/storage_access.h** * Renamed from `src/tir/transform/storage_access.h`. * Updated include guards from `TVM_TIR_TRANSFORM_STORAGE_ACCESS_H_` to `TVM_S_TIR_TRANSFORM_STORAGE_ACCESS_H_`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * **src/s_tir/transform/tensorcore_infer_fragment.cc** * Renamed from `src/tir/transform/tensorcore_infer_fragment.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.InferFragment`. * **src/s_tir/transform/thread_storage_sync.cc** * Renamed from `src/tir/transform/thread_storage_sync.cc`. * Updated include path to `tvm/s_tir/transform.h`. * Changed namespace from `tvm::tir` to `tvm::s_tir`. * Updated pass name and FFI registration to `s_tir.ThreadSync`. * **tests/python/s_tir/transform/test_s_tir_transform_hoist_expression.py** * Renamed from `tests/python/tir-transform/test_tir_transform_hoist_expression.py`. * Updated imports from `tvm.tir` to `tvm.s_tir`. * Updated calls to `tvm.tir.transform.HoistExpression` to `tvm.s_tir.transform.HoistExpression`. * **tests/python/s_tir/transform/test_s_tir_transform_hoist_if.py** * Renamed from `tests/python/tir-transform/test_tir_transform_hoist_if.py`. * Updated imports from `tvm.te` to `tvm.te, s_tir`. * Updated calls to `tvm.tir.transform.HoistIfThenElse` to `tvm.s_tir.transform.HoistIfThenElse`. * **tests/python/s_tir/transform/test_s_tir_transform_inject_ptx_async_copy.py** * Renamed from `tests/python/tir-transform/test_tir_transform_inject_ptx_async_copy.py`. * Updated imports to include `tvm.s_tir`. * Updated calls to `tvm.tir.transform.InjectPTXAsyncCopy` and `tvm.tir.transform.MergeSharedMemoryAllocations` to use `s_tir.transform`. * **tests/python/s_tir/transform/test_s_tir_transform_inject_ptx_ldg32.py** * Renamed from `tests/python/tir-transform/test_tir_transform_inject_ptx_ldg32.py`. * Updated imports to include `tvm.s_tir`. * Updated calls to `tvm.tir.transform.InjectPTXLDG32` to `tvm.s_tir.transform.InjectPTXLDG32`. * **tests/python/s_tir/transform/test_s_tir_transform_lower_thread_all_reduce.py** * Renamed from `tests/python/tir-transform/test_tir_transform_lower_thread_all_reduce.py`. * Updated imports to include `tvm.s_tir`. * Updated calls to `tvm.tir.transform.LowerThreadAllreduce` to `tvm.s_tir.transform.LowerThreadAllreduce`. * **tests/python/s_tir/transform/test_s_tir_transform_merge_dynamic_shared_memory_allocations.py** * Renamed from `tests/python/tir-transform/test_tir_transform_merge_dynamic_shared_memory_allocations.py`. * Updated imports to include `tvm.s_tir`. * Updated calls to `tvm.tir.transform.MergeSharedMemoryAllocations` to `tvm.s_tir.transform.MergeSharedMemoryAllocations`. * **tests/python/s_tir/transform/test_s_tir_transform_profiling_instr.py** * Renamed from `tests/python/tir-transform/test_tir_transform_profiling_instr.py`. * Updated imports to include `tvm.s_tir`. * Updated calls to `tvm.tir.transform.InstrumentProfileIntrinsics` to `tvm.s_tir.transform.InstrumentProfileIntrinsics`. * **tests/python/s_tir/transform/test_s_tir_transform_renormalize_split_pattern.py** * Renamed from `tests/python/tir-transform/test_tir_transform_renormalize_split_pattern.py`. * Updated imports to include `tvm.s_tir`. * Updated calls to `tvm.tir.transform.RenormalizeSplitPattern` to `tvm.s_tir.transform.RenormalizeSplitPattern`. * **tests/python/s_tir/transform/test_s_tir_transform_rewrite_unsafe_select.py** * Renamed from `tests/python/tir-transform/test_tir_transform_rewrite_unsafe_select.py`. * Updated imports to include `tvm.s_tir`. * Updated calls to `tvm.tir.transform.RewriteUnsafeSelect` to `tvm.s_tir.transform.RewriteUnsafeSelect`. * **tests/python/s_tir/transform/test_s_tir_transform_thread_sync.py** * Renamed from `tests/python/tir-transform/test_tir_transform_thread_sync.py`. * Updated imports to include `tvm.s_tir`. * Updated calls to `tvm.tir.transform.ThreadSync` to `tvm.s_tir.transform.ThreadSync`. </details> <details> <summary><b>Using Gemini Code Assist</b></summary> <br> The full guide for Gemini Code Assist can be found on our [documentation page](https://developers.google.com/gemini-code-assist/docs/review-github-code), here are some quick tips. <b>Invoking Gemini</b> You can request assistance from Gemini at any point by creating a comment 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